Select Publications
NLP Methods for Extraction of Symptoms from Unstructured Data for Use in Prognostic COVID-19 Analytic Models
by Greg Silverman, Himanshu Sahoo, Nicholas Ingraham, Monica Lupei, Michael Puskarich, Michael Usher, Eric Murray, James Dries, Raymond Finzel, John Sartori, Gyorgy Simon, Genevieve Melton, Christopher Tignanelli, Serguei Pakhomov
Journal of Artificial Intelligence Research (JAIR), 2021
A fast, resource efficient, and reliable rule-based system for COVID-19 symptom identification
by Himanshu Sahoo, Greg Silverman, Nicholas Ingraham, Monica Lupei, Michael Puskarich, Raymond Finzel, John Sartori, Rui Zhang, Benjamin Knoll, Sijia Liu, Hongfang Liu, Genevieve Melton, Christopher Tignanelli, Serguei Pakhomov
Journal of the American Medical Informatics Association (JAMIA), 2021
Bespoke Processors for Applications with Ultra-low Area and Power Constraints
by Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori
IEEE Micro, Top Picks from Computer Architecture Conferences, 2018
Determining Application-specific Peak Power and Energy Requirements for Ultra-low-power Processors
by Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori
ACM Transactions on Computer Systems (TOCS), 2017.
Approximate Communication: Techniques for Reducing Communication Bottlenecks
by Filipe Betzel, Karen Khatamifard, Harini Suresh, David J. Lilja, John Sartori, and Ulya Karpuzcu
ACM Computing Surveys (CSUR), 2018
Automated Algorithmic Error Resilience Based on Outlier Detection [Featured Article]
by Amoghavarsha Suresh and John Sartori
IEEE Micro, Special Series on Harsh Chips, 2016
Enhancing the Efficiency of Energy-Constrained DVFS Designs
by Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori
IEEE Transactions on Very Large Integration Systems (TVLSI), 2013
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity [Best Paper Award]
by Xun Jian, John Sartori, Henry Duwe, and Rakesh Kumar
IEEE Computer Architecture Letters (CAL), 2013
Branch and Data Herding: Reducing Control and Memory Divergence for Error-tolerant GPU Applications
by John Sartori and Rakesh Kumar
IEEE Transactions on Multimedia (TMM) Special Issue on New Software / Hardware Paradigms for Error-tolerant Multimedia Systems, 2013
Exploiting Timing Error Resilience in Processor Architecture
by John Sartori and Rakesh Kumar
ACM Transactions on Embedded Computing Systems (TECS) Special Issue on Probabilistic Embedded Computing, 2012
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors
by Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012
A Scalable Symbolic Simulation Tool for Low-power Embedded Systems
by Subhash Sethumurugan, Shashank Hegde, Hari Cherupalli, and John Sartori
59th ACM/IEEE Design Automation Conference (DAC), San Francisco, July 2022.
Polymer-based Acoustic Wave Sensor Using Hot Embossing Technique
by Jungyoon Kim, Tianyi Zhang, Quan Guan, John Sartori, Lauren Linderman, Vuk Mandic, and Tianhong Cui
21st International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers), June 2021.
Property-driven Automatic Generation of Reduced-ISA Hardware
by Nathaniel Bleier, Rakesh Kumar, and John Sartori
58th ACM/IEEE Design Automation Conference (DAC), San Francisco, December 2021.
Designing a Cost-Effective Cache Replacement Policy using Machine Learning
by Subhash Sethumurugan, Jieming Yin, and John Sartori
27th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea, February 2021.
Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems
by Shashank Hegde, Subhash Sethumurugan, Hari Cherupalli, Henry Duwe, and John Sartori
26th IEEE/SIGDA Asia and South Pacific Design and Automation Conference (ASPDAC), Tokyo, Japan, January 2021.
Enhancing Workload-dependent Voltage Scaling for Energy-efficient, Ultra-low-power Embedded Systems
by Veni Mohan, Akhilesh Iyer, and John Sartori
55th ACM/IEEE Design Automation Conference (DAC), San Francisco, June 2018.
Software-based Gate-level Information Flow Security for IoT Systems
by Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori
50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Boston, MA, October 2017
Scalable N-worst Algorithms for Dynamic Timing and Activity Analysis
by Hari Cherupalli and John Sartori
International Conference on Computer-Aided Design (ICCAD), Irvine, CA, November 2017
Approximate Communication -- Enhancing Compressibility Through Data Approximation
by Harini Suresh, Shashank Hegde, and John Sartori
15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), Seoul, Korea, October 2017
Bespoke Processors for Applications with Ultra-low Area and Power Constraints
by Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori
44th ACM/IEEE International Symposium on Computer Architecture (ISCA), Toronto, ON, June 2017.
A Scalable Approach to Hardware-Software Co-Analysis Using Symbolic Simulation
by Hari Cherupalli, Henry Duwe, and John Sartori
54th ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2017.
Determining Application-specific Peak Power and Energy Requirements for Ultra-low-power Processors [Best Paper Award]
by Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori
22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, April 2017.
Enabling Effective Module-oblivious Power Gating for Embedded Processors
by Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori
23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, February 2017.
Automated Error Prediction for Approximate Sequential Circuits
by Amrut Kapare, Hari Cherupalli, and John Sartori
International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2016
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems
by Hari Cherupalli, Rakesh Kumar, and John Sartori
43rd ACM/IEEE International Symposium on Computer Architecture (ISCA), Seoul, Korea, June 2016.
Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions
by Hari Cherupalli and John Sartori
International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2015.
Software Canaries: Software-based Path Delay Fault Testing for Variation-aware Energy-efficient Design
by John Sartori and Rakesh Kumar
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA, August 2014.
Exploiting Workload-dependent Timing Slack for Energy Efficiency in Embedded Systems
by John Sartori and Rakesh Kumar
51st ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2014.
Automated Algorithmic Error Resilience for Structured Grid Problems based on Outlier Detection
by Amoghavarsha Suresh and John Sartori
IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Orlando, FL, February 2014.
Low Power, Low Storage Overhead Chipkill Correct via Multi-Line Error Correction (Multi-ECC)
by Xun Jian, John Sartori, Henry Duwe, Vilas Sridharan, and Rakesh Kumar
26th ACM/IEEE Supercomputing Conference (SC), Denver, CO, November 2013.
Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits
by Wei-Ting Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori
31st IEEE International Conference on Computer Design (ICCD), Asheville, NC, October 2013.
Compiling for Energy Efficiency on Timing Speculative Processors
by John Sartori and Rakesh Kumar
49th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012.
Exploiting Application-Level Error Tolerance in Software Design for Stochastic Processors [Invited]
by Joseph Sloan, John Sartori, and Rakesh Kumar
49th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012.
Power Balanced Pipelines [Nominated for Best Paper Award]
by John Sartori, Ben Ahrens, and Rakesh Kumar
18th IEEE International Symposium on High-Performance Computer Architecture (HPCA), New Orleans, LA, February 2012.
Architecting Processors to Allow Voltage/Reliability Tradeoffs [Best Paper Award]
by John Sartori and Rakesh Kumar
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Taipei, Taiwan, October 2011.
Stochastic Computing: Embracing Errors in Architecture and Design of Processors and Applications [Invited]
by John Sartori, Joseph Sloan, and Rakesh Kumar
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Taipei, Taiwan, October 2011.
Compiling for Timing Error Resilient Processors
by John Sartori and Rakesh Kumar
SRC TECHCON Conference 2011 (TECHCON), Austin, TX, September 2011.
On the Efficacy of NBTI Mitigation Techniques
by Tuck-Boon Chan, John Sartori, Puneet Gupta, and Rakesh Kumar
Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011.
Energy-Efficient Architectures for Timing Error-Tolerant Processors [Invited]
by John Sartori and Rakesh Kumar
International Conference on Energy Aware Computing 2010 (ICEAC), Cairo, Egypt, December 2010.
Optimal Power/Performance Pipelining for Error Resilient Processors
by Nicolas Zea, John Sartori, Ben Ahrens, and Rakesh Kumar
28th IEEE International Conference on Computer Design 2010 (ICCD), Amsterdam, Netherlands, October 2010.
Recovery-driven Design
by John Sartori, Rakesh Kumar, Seokhyeong Kang, and Andrew Kahng
SRC TECHCON Conference 2010 (TECHCON), Austin, TX, September 2010.
Recovery-driven Design: A Methodology for Power Minimization for Error Tolerant Processor Modules
by Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori
47th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2010.
Overscaling-friendly Timing Speculation Architectures
John Sartori and Rakesh Kumar
20th ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), Providence, RI, May 2010.
Variation-Aware Speed Binning of Multi-core Processors
John Sartori, Aashish Pant, Rakesh Kumar, and Puneet Gupta
11th ACM/IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2010.
Scalable Stochastic Processors
Sriram Narayanan, John Sartori, Rakesh Kumar, and Doug Jones
Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2010.
(6-page version)
Designing Soft Architectures from the Ground Up (a Design Methodology to Allow Voltage/Reliability Tradeoffs in Processors)
by Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori
16th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Bangalore, India, January 2010.
Low Overhead, High-Speed Multi-core Barrier Synchronization
by John Sartori and Rakesh Kumar
International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC), Pisa, Italy, January 2010.
Slack Redistribution for Graceful Degradation Under Voltage Overscaling [10-year Retrospective Most Influential Paper Award]
by Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori
15th IEEE/SIGDA Asia and South Pacific Design and Automation Conference (ASPDAC), Taipei, Taiwan, January 2010.
Three Scalable Approaches to Improving Many-core Throughput for a Given Peak Power Budget
by John Sartori and Rakesh Kumar
International Conference on High Performance Computing (HiPC), Kochi, India, December 2009.
Distributed Peak Power Management for Many-core Architectures
by John Sartori and Rakesh Kumar
Design, Automation, and Test in Europe (DATE), Nice, France, March 2009.
(6-page version)
Stochastic Computing [Invited]
by John Sartori and Rakesh Kumar
Foundations and Trends in Electronic Design Automation (FnTEDA), 2011.