Journal Publications
2020 and in Press...

Z. Zhang and K.K. Parhi, "M3U: Minimum Mean Minimum Uncertainty Feature Selection For Multiclass Classification," Springer Journal of Signal Processing Systems (JSPS), 92(1), pp. 922, Jan. 2020

B. Sen, G.A. Bernstein, B.A. Mueller, K.R. Cullen and K.K. Parhi, "SubGraph Entropy based Network Approaches for Classifying Adolescent ObsessiveCompulsive Disorder from RestingState Functional MRI," Neuroimage: Clinical, 20, Article 102208, 2020 (Supplementary Information)

C. Cheng and K.K. Parhi, "Fast 2D Convolution Algorithms for Convolutional Neural Networks," IEEE Transactions on Circuits and Systems, PartI: Regular Papers, 67(5), pp. 16781691, May 2020

X. Liu and K.K. Parhi, "Molecular and DNA Artificial Neural Networks via Fractional Coding," IEEE Transactions on Biomedical Circuits and Systems, 14(3), pp. 490503, June 2020 (Supplementary Material)

L. Ge and K.K. Parhi, "Classification using Hyperdimensional Computing: A Review," IEEE Circuits and Systems Magazine, 20(2), pp. 3047, June 2020

S.V.S. Avvaru, Z. Zeng and K.K. Parhi, "Homogeneous and Heterogeneous FeedForward XOR Physical Unclonable Functions," IEEE Transactions on Information Forensics and Security, 15(12), pp. 24852498, Dec. 2020

Q. Zhang, Y. Chen, S. Li, X. Zeng and K.K. Parhi, "A HighPerformance Stochastic LDPC Decoder Architecture via Correlation Analysis," IEEE Transactions on Circuits and Systems, PartI: Regular Papers, to appear

B. Sen and K.K. Parhi, "Predicting Biological Gender and Intelligence from fMRI via Dynamic Functional Connectivit," IEEE Transactions on Biomedical Engineering, ( Supplementary Information) to appear
2019

K.K. Parhi and Y. Liu, "Computing Arithmetic Functions Using Stochastic Logic by Series Expansion," IEEE Transactions on Emerging Technologies in Computing (TETC), 7(1), pp. 4459, March 2019

S. Koteshwara, A. Das and K.K. Parhi, "Architecture Optimization and Performance Comparison of NonceMisuse Resistant Authenticated Encryption Algorithms," IEEE Transactions on VLSI Systems, 27(5), pp. 10531066, May 2019

B. Sen, S.H. Chu and K.K. Parhi, "Ranking Regions, Edges and Classifying Tasks in Functional Brain Graphs by SubGraph Entropy," Scientific Reports, Vol. 9, Article 7628, May 2019 ( Supplementary Information)

K.K. Parhi and Z. Zhang, "Discriminative Ratio of Spectral Power and Relative Power Features Derived via FrequencyDomain Model Ratio (FDMR) with Application to Seizure Prediction," IEEE Transactions on Biomedical Circuits and Systems, 13(4), pp. 645657, August 2019

H. Bogunovic, F. Venhuizen, S. Klimscha, S. Apostolopoulos, A. BabHadiashar, U. Bagci, M. Faisal Beg, L. Bekalo, Q. Chen, C. Ciller, K. Gopinath, A.K. Gostar, K. Jeon, Z. Ji, S.H. Kang, D.D. Koozekanani, D. Lu, D. Morley, K.K. Parhi, H.S. Park, A. Rashno, M. Sarunic, S. Shaikh, J. Sivaswamy, R. Tennakoon, S. Yadav, S. De Zanet, S.M. Waldstein, B.S. Gerendas, C. Klaver, C.I. Sanchez, U. SchmidtErfurth, "RETOUCH  The Retinal OCT Fluid Detection and Segmentation Benchmark and Challenge," IEEE Transactions on Medical Imaging, 38(8), pp. 18581874, August 2019

Z. Zhang and K.K. Parhi, "MUSE: Minimum Uncertainty and Sample Elimination Based Binary Feature Selection," IEEE Transactions on Knowledge and Data Engineering (TKDE), 31(9), pp. 17501764, Sept. 2019
2018

S. Koteshwara, C.H. Kim and K.K. Parhi, "KeyBased Dynamic Functional Obfuscation of Integrated Circuits using SequentiallyTriggered ModeBased Design," IEEE Trans. Information Forensics and Security (TIFS), 13(1), pp. 7993, Jan. 2018

S. Chu, K.K. Parhi and C. Lenglet, "Functionspecific and Enhanced Brain Structural Connectivity Mapping via Joint Modeling of Diffusion and Functional MRI," Scientific Reports, Vol. 8, Article 4741, March 2018 ( Supplementary Material )

A. Rashno, D.D. Koozekanani, P.M. Drayna, B. Nazari, S. Sadri, H. Rabbani, and K.K. Parhi, "FullyAutomated Segmentation of Fluid/Cyst Regions in Optical Coherence Tomography Images with Diabetic Macular Edema using Neutrosophic Sets and Graph Algorithms," IEEE Trans. Biomedical Engineering, 65(5), pp. 9891001, May 2018 (Supplementary Material)

S.A. Salehi, X. Liu, M.D. Riedel, and K.K. Parhi, "Computing Mathematical Functions using DNA via Fractional Coding," Scientific Reports, Vol. 8, Article 8312, May 2018 ( Supplementary Material)

Y. Liu and K.K. Parhi, "LinearPhase Lattice FIR Digital Filter Architectures using Stochastic Logic," Springer Journal of Signal Processing Systems (JSPS), 90(5), pp. 791803, May 2018

Y. Lao and K.K. Parhi, "Canonic Composite Length RealValued FFT," Springer Journal of Signal Processing Systems (JSPS), 90(10), pp. 14011414, October 2018

M. Garrido, N.K. Unnikrishnan and K.K. Parhi, "A Serial Commutator Fast Fourier Transform Architecture for RealValued Signals," IEEE Trans. on Circuits and Systems, PartII: Express Briefs, 65(11), pp. 16931697, Nov. 2018

K.K. Parhi, "Stochastic Logic Implementations of Polynomials with All Positive Coefficients by Expansion Methods," IEEE Transactions on Circuits and Systems, PartII: Transactions Briefs, 65(11), pp. 16981702, Nov. 2018

S. Koteshwara and K.K. Parhi, "IncrementalPrecision based Feature Computation and MultiLevel Classification for LowEnergy InternetofThings," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 8(4), pp. 822835, Dec. 2018
2017

B. Yuan and K.K. Parhi, "LLRbased SuccessiveCancellation List Decoder for Polar Codes with Multibit Decision," IEEE Transactions on Circuits and Systems, PartII: Transactions Briefs, 64(1), pp. 2125, Jan. 2017

S.A. Salehi, K.K. Parhi and M.D. Riedel, "Chemical Reaction Networks for Computing Polynomials," ACS Synthetic Biology, 6(1), pp. 7683, Jan. 2017

Y. Lao, B. Yuan, C.H. Kim and K.K. Parhi, "Reliable PUFbased Local Authentication with SelfCorrection," IEEE Trans. Computer Aided Design, 36(2), pp. 201213, Feb. 2017

B. Yuan and K.K. Parhi, "VLSI Architectures for the Restricted Boltzmann Machine," ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(3), Article 35, May 2017

Y. Liu and K.K. Parhi, "Computing Polynomials using Unipolar Stochastic Logic," ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(3), Article 42, May 2017

K.K. Parhi, "Takao Nishitani: An Outstanding Researcher, Technical Leader and Mentor," IEEE SolidState Circuits Magazine, 9(2), Spring 2017

Y. Lao and K.K. Parhi, "Canonic FFT FlowGraphs for RealValued Even/Odd Symmetric Inputs," EURASIP Journal on Advances in Signal Processing, 2017:45, June 2017

A. Rashno, B. Nazari, D. D. Koozekanani, P.M. Drayna, S. Sadri, H. Rabbani and K.K. Parhi, "FullyAutomated 2D and 3D Segmentation of Fluid Regions in Exudative AgeRelated Macular Degeneration Subjects: Kernel Graph Cut in Neutrosophic Domain," PloS ONE, 12(10), e0186949, Oct. 2017
2016

T. Xu, K.R. Cullen, B. Mueller, M.W. Schreiner, K.O. Lim, S.C. Schulz, and K.K. Parhi, "Network Analysis of Functional Brain Connectivity in Borderline Personality Disorder Using RestingState fMRI," NeuroImage: Clinical, 11, pp. 302315, 2016

Z. Zhang and K.K. Parhi, "LowComplexity Seizure Prediction From iEEG/sEEG using Spectral Power and Ratios of Spectral Power," IEEE Transactions on Biomedical Circuits and Systems, 10(3), pp. 693706, June 2016

Y. Liu and K.K. Parhi, "Architectures for Recursive Digital Filters Using Stochastic Computing," IEEE Transactions on Signal Processing, 64(14), pp. 37053718, July 15, 2016

Y. Wang, B. Yuan, and K.K. Parhi, "Improved BER Performance with Rotated Head Array and 2D Detector in TwoDimensional Magnetic Recording," IEEE Trans. Magnetics, 52(7), Article#3001706, July 2016

T. Xu, M. Stephane and K.K. Parhi, "Abnormal Neural Oscillations in Schizophrenia Assessed by Spectral Power Ratio of MEG during Word Processing," IEEE Transactions on Neural Systems and Rehabilitation Engineering, 24(11), pp. 11481158, Nov. 2016

S. Roychowdhury, D.D. Koozekanani, S.N. Kuchinka, and K.K. Parhi, "Optic Disc Boundary and Vessel Origin Segmentation of Fundus Images," IEEE Journal of Biomedical and Health Informatics, 20(6), pp. 15621574, Nov. 2016 (Supplementary Material)

Y. Lao, Q. Tang, C.H. Kim and K.K. Parhi, "Beat Frequency Detector based HighSpeed TRNGs: Statistical Modeling and Analysis," ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(1), Article 9, Dec. 2016
2015

Y. Lao and K.K. Parhi, "Obfuscating DSP Circuits via HighLevel Transformations," IEEE Transactions on VLSI Systems, 23(5), pp. 819830, May 2015

S. Roychowdhury, D.D. Koozekanani and K.K. Parhi, "Blood Vessel Segmentation of Fundus Images by Major Vessel Extraction and SubImage Classification," IEEE Journal of Biomedical and Health Informatics, 19(3), pp. 11181128, May 2015

S. Roychowdhury, D.D. Koozekanani and K.K. Parhi, "Iterative Vessel Segmentation of Fundus Images," IEEE Transactions on Biomedical Engineering, 62(7), pp. 17381749, July 2015 (Supplementary Material)

M. Bandarabadi, J. Rasekhi, C.A. Teixeira, T.I. Netoff, K.K. Parhi, and A. Dourado, "Early Seizure Detection using Neuronal Potential Similarity: A Generalized LowComplexity and Robust Measure," International Journal of Neural Systems (IJNS), 25(5), pp: 1550019:118, Aug. 2015

S.A. Salehi, H. Jiang, M.D. Riedel, and K.K. Parhi, "Molecular Sensing and Computing Systems (Invited Paper)," IEEE Transactions on Molecular, Biological, and MultiScale Communications, 1(3), pp. 249264, Sept. 2015

B. Yuan and K.K. Parhi, "LowLatency SuccessiveCancellation List Decoders for Polar Codes with Multibit Decision," IEEE Transactions on VLSI Systems, 23(10), pp. 22682280, October 2015
2014

K.K. Parhi and M. Ayinala, "LowComplexity Welch Power Spectral Density Computation," IEEE Trans. Circuits and SystemsI: Regular Papers, 61(1), pp. 172182, Jan. 2014

R. Liu, T.L. Kung and K.K. Parhi, "Impulse Noise Correction in OFDM Systems," Springer Journal of Signal Processing Systems, 74(2), pp. 245262, Feb. 2014

C. Zhang and K.K. Parhi, "Latency Analysis and Architecture Design of Simplified SC Polar Decoders," IEEE Trans. Circuits and SystemsII: Transactions Briefs, 61(2), pp. 115119, Feb. 2014

B. Yuan and K.K. Parhi, "LowLatency SuccessiveCancellation Polar Decoder Architectures using 2bit Decoding," IEEE Trans. Circuits and SystemsI: Regular Papers, 61(4), pp. 12411254, Apr. 2014

Y. Lao and K.K. Parhi "Statistical Analysis of MUXbased Physical Unclonable Functions," IEEE Trans. on Computer Aided Design, 33(5), pp. 649662, May 2014

S. Roychowdhury, D.D. Koozekanani and K.K. Parhi, "DREAM: Diabetic Retinopathy Analysis using Machine Learning," IEEE Journal of Biomedical and Health Informatics, 18(5), pp. 17171728, Sept. 2014, [Journal Cover]

Y. Wang, B. Yuan, K.K. Parhi and R. Victora, "TwoDimensional Magnetic Recording using a Rotated Head Array and LDPC Code Decoding," IEEE Transactions on Magnetics, 50(11), November 2014

B. Yuan and K.K. Parhi, "Early Stopping Criteria for EnergyEfficient LowLatency BeliefPropagation Polar Code Decoders," IEEE Transactions on Signal Processing, 62(24), pp. 64966506, Dec. 15, 2014
2013

T.L. Kung and K.K. Parhi, "Semiblind FrequencyDomain Timing Synchronization and Channel Estimation for OFDM Systems," EURASIP Journal on Advances in Signal Processing , 2013(1), Jan. 2013

Y. Hu, and K.K. Parhi, "Design and Optimization of Multiplierless FIR Filters Using SubThreshold Circuits," Springer Journal of Signal Processing Systems , 70(3), pp. 259274, March 2013

T.L. Kung and K.K. Parhi, "Performance Evaluation of Variable Transmission Rate OFDM Systems via Network Source Coding," EURASIP Journal on Advances in Signal Processing, Vol. 2013(12), 2013

K.K. Parhi, "Comments on "LowEnergy CSMT Carry Generators and Binary Adders"" IEEE Trans. VLSI Systems, 21(4), p. 791, April 2013

T. Xu, M. Stephane, and K.K. Parhi, "Multidimensional Analysis of Abnormal Neural Oscillations Associated with Lexical Processing in Schizophrenia," Clinical EEG & Neuroscience, 44(2), pp. 135143, April 2013

C. Zhang and K.K. Parhi, "LowLatency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder," IEEE Trans. Signal Processing, 61(10), pp. 24292441, May 15, 2013

H. Jiang, S.A. Salehi, M.D. Riedel, and K.K. Parhi, "DiscreteTime Signal Processing with DNA" American Chemical Society (ACS) Synthetic Biology, 2(5), pp. 245254, 2013

S.A. Salehi, R.Amirfattahi, and K.K. Parhi, "Pipelined Architectures for RealValued FFT and HermitianSymmetric IFFT with Real Datapaths," IEEE Trans. Circuits and SystemsII: Transactions Briefs, 60(8), pp. 507511, Aug. 2013

M. Ayinala and K.K. Parhi, "FFT Architectures for Realvalued Signals based on Radix2^3 and Radix2^4 algorithms," IEEE Trans. Circuits and SystemsI: Regular Papers, 60(9), pp. 24222430, Sept. 2013

K.K. Parhi, "Hierarchical Folding and Synthesis of Iterative DataFlow Graphs," IEEE Trans. Circuits and SystemsII: Transactions Briefs, 60(9), pp. 597601, Sept. 2013

T. Kung and K.K. Parhi, "Optimized Joint Timing Synchronization and Channel Estimation for Communications Systems with Multiple Transmit Antennas," EURASIP Journal on Advances in Signal Processing, 2013(139), 2013

M. Ayinala, Y. Lao, and K.K. Parhi, "An InPlace FFT Architecture for RealValued Signals," IEEE Trans. Circuits and SystemsII: Transactions Briefs, 60(10), pp. 652656, Oct. 2013
2012

A.E. Cohen, J.H. Lin, and K.K. Parhi, "Variable Data Rate (VDR) Network Congestion Control (NCC) Applied to Voice/Audio Communication," Computer Networks , Elsevier, 56(4), pp. 13431356, March 2012

H. Jiang, M.D. Riedel, and K.K. Parhi, "Digital Signal processing with Molecular Reactions," IEEE Design & Test Magazine , (Special Issue on BioDesign Automation in Synthetic Biology), 29(3), pp. 2131, May/June 2012

M. Ayinala, M.J. Brown and K.K. Parhi, "Pipelined Parallel FFT Architectures via Folding Transformation", IEEE Trans. VLSI Systems , pp. 10681081, 20(6), June 2012

C. Zhang, and K.K. Parhi, "A NetworkEfficient NonBinary QCLDPC Decoder Architecture", IEEE Trans. Circuits and SystemsI: Regular Papers , 59(6), pp. 13591371, June 2012

T. Kung, and K.K. Parhi, "Optimized Joint Timing Synchronization and Channel Estimation for OFDM Systems," IEEE Wireless Communications Letters , 1(3), pp. 149152, June 2012

H.A. Patil, M.C. Madhavi, and K.K. Parhi, "Static and Dynamic Information Derived from Source and System Features for Person Recognition from Humming," Springer International Journal of Speech Technology, , 15(3), pp. 393406, September 2012
2011

A.E. Cohen and K.K. Parhi, "Secure Variable Data Rate Transmission," IEEE Trans. Circuits and SystemsII: Transactions Briefs , 58(2), pp. 100104, Feb. 2011

M. Ayinala and K.K. Parhi, "HighSpeed Parallel Architectures for Linear Feedback Shift Registers", IEEE Trans. Signal Processing , 59(9), pp. 44594469, Sept. 2011

Y. Park, L. Luo, K.K. Parhi and T. Netoff, "Seizure Prediction with Spectral Power of EEG Using CostSensitive Support Vector Machines," Epilepsia , 52(10), pp. 17611770, Oct. 2011, (Supplementary Material) [Journal Cover]

R. Liu and K.K. Parhi, "Power Reduction in FrequencySelective FIR Filters under Voltage Overscaling," IEEE Journal on Emerging Technologies in Circuits and Systems, 1(3), pp. 343356, Sept. 2011

A.E. Cohen and K.K. Parhi, "Architecture Optimizations for the RSA Public Key Cryptosystem: A Tutorial", IEEE Circuits and Systems Magazine , 11(4), pp. 2434, Nov. 2011
2010

D. Oh and K.K. Parhi, "Minsum Decoder Architecture with Reduced WordLength for LDPC Codes", IEEE Trans. Circuits and SystemsI: Regular Papers, 57(1), pp. 105115, Jan. 2010

D. Oh and K.K. Parhi, "LowComplexity Switch Networks for Reconfigurable LDPC Decoders", IEEE Trans. VLSI Systems , 18(1), pp. 8594, Jan. 2010

Y. Liu, T. Zhang and K.K. Parhi, "Computation Error Analysis in Digital Signal Processing System with Overscaled Supply Voltage", IEEE Trans. VLSI Systems , 18(4), pp. 517526, Apr. 2010

A.E. Cohen and K.K. Parhi, "Fast Elliptic Curve Cryptography Acceleration for GF(2^m) on 32Bit Processors", Springer Journal of Signal Processing Systems , 60(1), pp. 3145, July 2010
2009

E. Saberinia, J. Tang, A.H. Tewfik, and K.K. Parhi, "Pulsed OFDM Modulation for Ultra Wideband Communications", IEEE Trans. on Vehicular Technology , 58(2), pp. 720726, Feb. 2009

S. Park, K.K. Parhi, and S.C. Park, "Probabilistic Spherical Detection and VLSI Implementation for Multiple Antenna Systems", IEEE Trans. Circuits and SystemsI: Regular Papers, 56(3), pp. 685698, March 2009

J. Chen, Y. Gu and K.K. Parhi, "Novel FEXT Cancellation and Equalization for HighSpeed Ethernet Transceivers", IEEE Trans. Circuits and SystemsI: Regular Papers, 56(6), pp. 12721285, June 2009

D. Oh and K.K. Parhi, "LowComplexity Decoder Architecture for Lowdensity Parity Check Codes", Journal of VLSI Signal Processing Systems , 56, pp. 217228, June 2009

R. Liu and K.K. Parhi, "LowLatency LowComplexity Architectures for Viterbi Decoders", IEEE Trans. Circuits and SystemsI: Regular Papers, 56(10), pp. 23152324, Oct. 2009

A.E. Cohen and K.K. Parhi, "A LowComplexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBaseT) Ethernet", IEEE Trans. Signal Processing, 57(10), pp. 40854094, Oct. 2009

M. Garrido, K.K. Parhi, and J. Grajal, "A Pipelined FFT Architecture for RealValued Signals", IEEE Trans. Circuits and SystemsI: Regular Papers, 56(12), pp. 26342643, Dec. 2009
2008

C. Cheng and K.K. Parhi, "HighSpeed VLSI Implementation of 2D Discrete Wavelet Transform", IEEE Trans. on Signal Processing, 56(1), pp. 393403, Jan. 2008

Y. Gu and K.K. Parhi, "Design of Parallel TomlinsonHarashima Precoders", IEEE Trans. Circuits and SystemsII: Express Briefs, 55(5), pp. 447451, May 2008

J. Chen, Y. Gu and K.K. Parhi, "Low Complexity ECHO And NEXT Cancellers for HighSpeed Ethernet Transceivers", IEEE Trans. Circuits and SystemsI: Regular Papers, 55(9), pp. 28272840, Oct. 2008

C. Cheng and K.K. parhi, "HardwareEfficient LowLatency Architecture for HighThroughput Rate Viterbi Decoders", IEEE Trans. Circuits and SystemsII: Express Briefs, 55(12), pp. 12541258, Dec. 2008
2007

K.J. Cho, J.S. Park, B.K. Kim, J.G. Chung and K.K. Parhi, "Design of a SampleRate Converter From CD to DAT Using Fractional Delay Allpass Filter", IEEE Trans. on Circuits and Systems, PartII: Express Briefs, 54(1), pp. 1923, Jan. 2007

Y. Gu and K.K. Parhi, "Pipelined Parallel Decision Feedback Decoders for HighSpeed Ethernet over Copper", IEEE Trans. on Signal Processing, 55(2), pp. 707715, Feb. 2007

C. Cheng and K.K. Parhi, "Low Cost Parallel FIR Filter Structures with 2Stage Parallelism", IEEE Trans. Circuits and SystemsI: Regular Papers, 54(2), pp. 280290, Feb. 2007

C. Cheng and K.K. Parhi, "LowCost Fast VLSI Algorithm for Discrete Fourier Transform", IEEE Trans. Circuits and SystemsI: Regular Papers, 54(4), pp. 791806, Apr. 2007

Y. Gu and K.K. Parhi, "HighSpeed Architecture Design of TomlinsonHarashima Precoders", IEEE Trans. Circuits and SystemsI: Regular Papers, 54(9), pp. 19291937, Sep. 2007

C. Cheng and K.K. Parhi, "HighThroughput VLSI Architecture for FFT Computation", IEEE Trans. Circuits and SystemsII: Express Briefs, 54(10), pp. 863867, Oct. 2007
2006

C. Cheng and K.K. Parhi, "Hardware Efficient Fast Computation of the Discrete Fourier Transform", Springer Journal of VLSI Signal Processing, pp. 159171, 42(2), Feb. 2006

Y. Gu and K.K. Parhi, "Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper", Journal of VLSI Signal Processing Systems, 44(3), pp. 211221, March 2006

L. Gao and K.K. Parhi, "Models for Architectural Power and Power Grid Noise Analysis on Data Bus", Journal of VLSI Signal Processing Systems, 44(2), pp. 2546, August 2006

J.H. Lin and K.K. Parhi, "Parallelization of Context Based Adaptive Binary Arithmetic Coders", IEEE Trans. on Signal Processing, 54(10), pp. 37023711, Oct. 2006

C. Cheng and K.K. Parhi, "HighSpeed Parallel CRC Implementation Based on Unfolding, Pipelining and Retiming", IEEE Trans. Circuits and SystemsII: Express Briefs, 53(10), pp. 10171021, Oct. 2006

X. Zhang and K.K. Parhi, "On the Optimum Constructions of Composite Field for the AES Algorithm", IEEE Trans. Circuits and SystemsII: Express Briefs, 53(10), pp. 11531157, Oct. 2006

C. Cheng and K.K. Parhi, "Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures", IEEE Trans. on Signal Processing, 54(11), pp. 44194434, Nov. 2006
2005

Y. Chen and K.K. Parhi, "On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes" Journal of VLSI Signal Processing Systems, 39(12), pp. 3547, Jan. 2005

X. Zhang and K.K. Parhi, "Fast Factorization Architecture in SoftDecision ReedSolomon Decoding", IEEE Trans. on VLSI Systems, 13(4), pp. 413426, Apr. 2005

K.K. Parhi, "Design of MultiGigabit Multiplexer Loop Based Decision Feedback Equalizers", IEEE Trans. on VLSI Systems, 13(4), pp. 489493, Apr. 2005

C. Cheng and K.K. Parhi, "A Novel Systolic Array Structure for DCT", IEEE Trans. on Circuits and Systems, PartII: Express Briefs, 52(5), pp. 366369, July 2005

X. Zhang and K.K. Parhi, "HighSpeed Architectures for Parallel Long BCH Encoders", IEEE Trans. on VLSI Systems, 13(7), pp. 872877, July 2005
2004

Z. Chi, L. Song and K.K. Parhi, "On the Performance/Complexity Tradeoff in Block Turbo Decoder Design," IEEE Communications Letters, Vol. 52, No. 2, pp. 173175, Feb. 2004

K.K. Parhi, "An Improved Pipelined MSBFirst AddCompareSelect Unit Structure for Viterbi Decoders", IEEE Trans. on Circuits and Systems, PartI: Regular Papers, 51(3), pp. 504511, March 2004

K. K. Parhi, "Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders", IEEE Trans. on Circuits and Systems, PartI: Regular Papers, 51(3), pp. 512516, March 2004

T. Zhang and K.K. Parhi, "Joint (3,k)regular LDPC Code and Decoder/Encoder Design", IEEE Trans. Signal Processing, 52(4), pp. 10651079, April 2004

K.J. Cho, K.C. Lee, J.G. Chung, and K.K. Parhi, "Design of LowError Fixed Width Modified Booth Multiplier", IEEE Trans. on VLSI Systems, 12(5), pp. 522531, May 2004

J. Kong and K.K. Parhi, "LowLatency Architectures for HighThroughput Viterbi Decoders", IEEE Trans. on VLSI Systems, 12(6), pp. 642651, June 2004

Y. Chen and K.K. Parhi, "Small Area Parallel Chien search Architectures for Long BCH Codes", IEEE Trans. on VLSI Systems, 12(5), pp. 545549, May 2004

Y. Chen and K.K. Parhi, "Overlapped Message Passing of QuasiCyclic LowDensity Parity Check Codes", IEEE Trans. on Circuits and Systems, PartI: Regular Papers, 51(6), pp. 11061113, June 2004

J. Ma and K.K. Parhi, "Pipelined CORDIC Based StateSpace Orthogonal Recursive Digital Filters using Matrix LookAhead", IEEE Trans. Signal Processing, 52(7), pp. 21022119, July 2004

V. Sundararajan, S. Sapatnekar and K.K. Parhi, "A New Approach for Integration of MinArea Retiming and MinDelay Padding for Simultaneously Addressing Short Path and Long Path constraints", ACM Trans. on TODAES, 9(3), pp. 273289, July 2004

C. Cheng and K.K. Parhi, "Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution", IEEE Trans. on Circuits and Systems, PartI: Regular Papers, 51(8), pp. 14921500, Aug. 2004

X. Zhang and K.K. Parhi, "HighSpeed VLSI Architectures for the AES Algorithm", IEEE Trans. on VLSI Systems, 12(9), pp. 957967, Sep. 2004

Z. Chi, Z. Wang and K.K. Parhi, "On the Better Protection of Short Frame Turbo Codes", IEEE Trans. on Communications, 52(9), pp. 14351439, Sept. 2004
2003

T. Sansaloni, J. Valls and K.K. Parhi, "DigitSerial Complex Number Multipliers on FPGAs", Journal of VLSI Signal Processing, Vol. 33(12), pp. 105115, Jan. 2003

Z. Wang and K.K. Parhi, "Performance Improvement and Implementation Issues of Turbo/SOVA Decoders", IEEE Trans. on Communications, Vol. 51(4), pp. 570579, April 2003

T. Zhang and K.K. Parhi, < "An FPGA Implementation of (3,6) Regular LowDensity ParityCheck Code Decoder", Eurasip Journal on Applied Signal Processing, 2003(6), pp. 530542, May 2003

V. Sundararajan and K.K. Parhi, "Synthesis of Minimum Area Folded Architectures for Rectangular MultiDimensional Multirate DSP Systems", IEEE Trans. on Signal Processing, 51(7), pp. 19541965, July 2003

Y.N. Chang and K.K. Parhi, "An Efficient Pipelined FFT Implementation", IEEE Trans. on Circuits and Systems: PartII: Analog and Digital Signal Processing, Vol. 50(6), pp. 322325, June 2003

B. Sahoo and K.K. Parhi, "A Low Power Correlator for CDMA Wireless Systems", Journal of VLSI Signal Processing, 35(1), pp. 105112, August 2003

L. Gao, K.K. Parhi and J. Ma, "Relaxed AnnihilationReordering LookAhead QRDRLS Adaptive Filters", Journal of VLSI Signal Processing, Vol. 35(2), pp. 119135, Sept. 2003

J. Kong and K.K. Parhi, "Interleaved Convolutional Code and its Viterbi Decoder Architecture", EURASIP Journal on Applied Signal Processing, Vol. 2003(13), pp. 13281334, 2003

Y. Chen and K.K. Parhi, "Low Complexity Decoding Algorithms of Block Turbo Coded System" with Antenna Diversity, EURASIP Journal on Applied Signal Processing, Vol. 2003(13), pp. 13351345, 2003

S.M. Kim, J.G. Chung and K. K. Parhi, "Low error CSD FixedWidth Multiplier with Efficient Sign Extension", IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing, 50(3), pp. 984993, December 2003
2002

W.L. Freking and K.K. Parhi, "PerformanceScalable Array Architectures for Modular Multiplication", Journal of VLSI Signal Processing Systems, 31(2), pp. 101116, April 2002

V. Sundararajan, S. Sapatnekar and K.K. Parhi, "Fast and Exact Transistor Sizing Based on Iterative Relaxation", IEEE Trans. on CAD, 21(5), pp. 568581, May 2002

M. Kuhlmann and K.K. Parhi, "PCORDIC: A Precomputation Based CORDIC Algorithm for the Circular Mode", Eurasip Journal on Applied Signal Processing, 2002(9), pp. 936943, Sept. 2002

J.G. Chung and K.K. Parhi, "Frequency spectrum based lowarea lowpower parallel FIR filter design", Eurasip Journal on Applied Signal Processing, 2002(9), pp. 944953, Sept. 2002

J. Valls, M. Kuhlmann, K.K. Parhi, "Evaluation of CORDIC Algorithms for FPGA design", Journal of VLSI Signal Processing, 32(3), pp. 207222, Nov. 2002

Z. Wang, Z. Chi and K.K. Parhi, "AreaEfficient High Speed Decoding Schemes for Turbo/MAP Decoders", IEEE Trans. on VLSI Systems, 10(12), pp. 902912, Dec. 2002

Z. Wang and K.K. Parhi, "OnLine Extraction of Soft Decoding Information and its Applications in VLSI Turbo Codes", IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing ,49(12), pp. 760769, Dec. 2002

X. Zhang and K.K. Parhi, "Hardware Implementation of Advanced Encryption Standard Algorithm", IEEE CAS Magazine, 2(4), pp. 2446, Dec. 2002

I. Ben Dhaou, K.K. Parhi and H. Tenhunen, "Energy Efficient Signaling in Deepsubmicron Technology", VLSI Design: Special Issue on Timing Analysis and Optimization for Deep SubMicron ICs, Vol. 15(3), pp. 563586, 2002
2001

J. Ma, K.K. Parhi and E.F. Deprettere, "A Unified Algebraic Transformation Approach for Parallel Recursive and Adaptive Filtering and SVD Algorithms", IEEE Trans. on Signal Processing, 49(2), pp. 424437, Feb. 2001

M. Kuhlmann and K.K. Parhi, "A Novel LowPower Shared Division and SquareRoot using the GST Algorithm", VLSI Design, 12(3), pp. 365376, 2001

M.E. Zervakis, V. Sundararajan and K.K. Parhi, "Vector Processing of Wavelet Coefficients for Robust Image Denoising", Journal of Image and Vision Computing, Elsevier, 19(7), pp. 435450, May 2001

T. Zhang and K.K. Parhi, "A Novel Systematic Design Approach for Mastrovito Multipliers over GF(2^m)", IEEE Trans. on Computers, 50(7), pp. 734749, July 2001

Z. Chi, J. Ma and K.K. Parhi, "Hybrid Annihilation Transformation (HAT) for Pipelining QRD Based Least Square Adaptive Filters", IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing, 48(7), pp. 661674, July 2001

K.K. Parhi, "LowPower Implementation of DSP Systems", IEEE Trans. on Circuits and Systems, PartI: Fundamental Theory and Applications, 48(10), pp. 12141224, October 2001

Z. Wang, H. Suzuki and K.K. Parhi, "Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders", Journal of VLSI Signal Processing, 29(3), pp. 209222, November 2001
2000

J.H. Satyanarayana and K.K. Parhi, "Theoretical Analysis of WordLevel Switching Activity in the Presence of Glitching and Correlation", IEEE Trans. on VLSI Systems, 8(2), pp. 148159, Apr. 2000

L. Song, K.K. Parhi, I. Kuroda, T. Nishitani, "Hardware/Software Codesign of Finite Field Datapath for LowEnergy ReedSolomon Codecs", IEEE Trans. on VLSI Systems, 8(2), pp. 160172, Apr. 2000

J. Satyanarayana and K.K. Parhi, "Power Estimation of Digital Datapaths using HEAT Tool", IEEE Design and Test Magazine, 17(2), pp. 101110, AprilJune 2000

Y.N. Chang, H. Suzuki and K.K. Parhi, "A 2 Mb/s 256State 10 mW Rate1/3 Viterbi Decoder," IEEE Journal of Solid State Circuits, Vol. 35, No. 6, pp. 826834, June 2000

J.G. Chung, H. Kim and K.K. Parhi, "AngleConstrained IIR Filter Pipelining for Reduced Roundoff Errors", IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing, 47(6), pp. 555559, June 2000

Y.N. Chang and K.K. Parhi, "HighPerformance DigitSerial Complex Multiplier", IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing, 47(6), pp. 570572, June 2000

A. Shalash and K.K. Parhi, "PowerEfficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications", Journal of VLSI Signal Processing, 25(3), pp. 199213, July 2000

J. Ma, K.K. Parhi and E.F. Deprettere, "AnnihilationReordering LookAhead Pipelined CORDIC Based RLS Adaptive Filters and Their Application to Adaptive Beamforming", IEEE Trans. on Signal Processing, 48(8), pp. 24142431, Aug. 2000

J. Ma, K.K. Parhi, G.J. Hekstra and E.F. Deprettere, "Efficient Implementations of Pipelined CORDIC Based IIR Digital Filters using Fast Orthonormal Microrotations", IEEE Trans. on Signal Processing, 48(9), pp. 27122716, Sep. 2000

J. Ma, K.K. Parhi and E.F. Deprettere, "Pipelined CORDIC Based Cascade Orthogonal IIR Digital Filters", IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing, 47(11), pp. 12381253, Nov. 2000

L. Gao and K.K. Parhi, "Hierarchical Pipelining and Folding of QRDRLS Adaptive Filters and Its Application to Digital Beamforming," IEEE Trans. on Circuits and Systems, PartII: Analog and Digital Signal Processing, 47(12), pp. 15031519, Dec. 2000
1999

H.R. Srinivas and K.K. Parhi, "A Radix 2 Shared Division/SquareRoot Algorithm and its VLSI Architecture," Journal of VLSI Signal Processing, 21(1), pp. 3760, May 1999

T.C. Denk and K.K. Parhi, "TwoDimensional Retiming [VLSI Design]," IEEE Trans. on VLSI Systems, 7(2), pp. 198211, June 1999

A.F. Shalash and K.K. Parhi, "MultiDimensional Carrierless AM/PM Systems for Digital Subscriber Loops," IEEE Trans. on Communications, 47(11), pp. 16551667, Nov. 1999

K.K. Parhi, "LowEnergy CSMT CarryGenerators and Binary Adders," IEEE Trans. on VLSI Systems, 7(4), pp. 450462, Dec. 1999
1998

S. Jain, L. Song and K.K. Parhi, "Efficient SemiSystolic VLSI Architectures for Finite Field Arithmetic," IEEE Trans. on VLSI Systems, 6(1), pp. 101113, March 1998

M. Majumdar and K.K. Parhi, "Design of Data Format Converters using TwoDimensional Register Allocation," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(4), pp. 504508, April 1998

L. Song and K.K. Parhi, "LowEnergy DigitSerial/Parallel Finite Field Multipliers", Journal of VLSI Signal Processing, 19(2), pp. 149166, June 1998

T.C. Denk and K.K. Parhi, "Exhaustive Scheduling and Retiming of Digital Signal Processing Systems," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(7), pp. 821838, July 1998

L. Montalvo, K.K. Parhi, and A. Guyot, "New SvobodaTung Division," IEEE Trans. on Computers, 47(9), pp. 10141020, Sept. 1998

Y.N. Chang, C.Y. Wang, and K.K. Parhi, "Heuristic LoopBased Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units," Journal of VLSI Signal Processing, 19(3), pp. 243256, Aug. 1998

K. Ito, L.E. Lucke and K.K. Parhi, "ILP Based CostOptimal DSP Synthesis with Module Selection and Data Format Conversion," IEEE Trans. on VLSI Systems, 6(4), pp. 582594, Dec. 1998

T.C. Denk and K.K. Parhi, "Synthesis of Folded Pipelined Architectures for Multirate DSP Algorithms," IEEE Trans. on VLSI Systems, 6(4), pp. 595607, Dec. 1998

Y.N. Chang, J.H. Satyanarayana and K.K. Parhi, "Systematic Design of HighSpeed and LowPower DigitSerial Multipliers," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(12), pp. 15851596, Dec. 1998
1997

H.R. Srinivas, K.K. Parhi, and L. Montalvo, "Radix2 Division with OverRedundant Quotient Selection," IEEE Trans. on Computers, 46(1), pp. 8592, Jan. 1997

T.C. Denk and K.K. Parhi, "VLSI Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms," IEEE Transactions on Circuits and Systems, Part  II: Analog and Digital Signal Processing, 44(2), pp. 129132, Feb. 1997

B. Fu and K.K. Parhi, "Generalized Multiplication Free Arithmetic Codes," IEEE Transactions on Communications, 45(5), pp. 497501, May 1997

K.J. Raghunath and K.K. Parhi, "Finite Precision Error Analysis of QRDRLS and STARRLS Adaptive Filters," IEEE Transactions on Signal Processing}, 45(5), pp. 11931209, May 1997

K. Ito and K.K. Parhi, "A Generalized Technique for Register Counting and its Application to CostOptimal DSP Architecture Synthesis," Journal of VLSI Signal Processing, 16(1), pp. 5772, May 1997

J.H. Satyanarayana and K.K. Parhi, "A Theoretical Approach to Estimation of Bounds on Power Consumption in Digital Multipliers," IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 44(6), pp. 473481, June 1997

D.A. Parker and K.K. Parhi, "Low Area/Power Parallel FIR Digital Filter Implementations," Journal of VLSI Signal Processing, 17(1), pp. 7592, Sept. 1997

Y. Li and K.K. Parhi, "STAR Recursive Least Square Lattice Adaptive Filters," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 44(12), pp. 10401054, December 1997
1996

T.C. Denk and K.K. Parhi, "Lower Bounds on Memory Requirements for Statically Scheduled DSP Programs," Journal of VLSI Signal Processing, 12(3), pp. 247264. June 1996

K.J. Raghunath, and K.K. Parhi, "Pipelined RLS Adaptive Filtering using Scaled Tangent Rotations (STAR)," IEEE Transactions on Signal Processing, 44(10), pp. 25912604, October 1996
1995

K.K. Parhi, "HighLevel Algorithm and Architecture Transformations for DSP Synthesis," Journal of VLSI Signal Processing, 9(1), pp. 121143, January 1995

C.Y. Wang, and K.K. Parhi, "HighLevel DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation," IEEE Transactions on Computer Aided Design, 14(3), pp. 274295, March 1995

J.G. Chung, and K.K. Parhi, "Scaled Normalized Lattice Digital Filters," IEEE Transactions on Circuits and Systems  Part II: Analog and Digital Signal Processing, 42(4), pp. 278282, April 1995

N.R. Shanbhag, and K.K. Parhi, "Pipelined Adaptive DFE Architectures using Relaxed LookAhead," IEEE Trans. on Signal Processing, 43(6), pp. 13681385, June 1995

H.R. Srinivas, and K.K. Parhi, "A Fast Radix4 Division Algorithm," IEEE Transactions on Computers, 44(6), pp. 826831, June 1995

J.G. Chung, H. Kim and K.K. Parhi, "Pipelined Lattice WDF Design for Wideband Filters," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 42(9), pp. 616618, September 1995

C.Y. Wang, and K.K. Parhi, "Resource Constrained Loop List Scheduler for DSP Algorithms," Journal of VLSI Signal Processing, 11(1/2), pp. 7596, October 1995

K. Ito and K.K. Parhi, "Determining the Minimum Iteration Period of an Algorithm," Journal of VLSI Signal Processing, 11(3), pp. 229244, December 1995
1994

K.K. Parhi, F.H. Wu, and K. Ganesan, "Sequential and Parallel Neural Network Vector Quantizers," IEEE Transactions on Computers, 43(1), pp. 104109, January 1994

J.G. Chung, and K.K. Parhi, "Pipelining of Lattice IIR Digital Filters," IEEE Transactions on Signal Processing, 42(4), pp. 751761, April 1994

L.E. Lucke, and K.K. Parhi, "Parallel Processing Architectures for RankOrder and Stack Filters," IEEE Transactions on Signal Processing, 42(5), pp. 11781189, May 1994

N.R. Shanbhag, and K.K. Parhi, "Finite Precision Analysis of the ADPCM Coder," IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing, 41(5), pp. 364368, May 1994

K.K. Parhi, "Calculation of Minimum Number of Registers in Arbitrary Life Time Chart," IEEE Circuits and Systems Transactions  Part II: Analog and Digital Signal Processing, 41(6), pp. 434436, June 1994

N.R. Shanbhag, and K.K. Parhi, "Corrections to "Finite Precision Analysis of the ADPCM Coder," IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing, 41(7), pp. 493, July 1994

G.B. Adams III, E.J. Coyle, L. Lin, L.E. Lucke, and K.K. Parhi, "Input Compression and Efficient VLSI Architectures for RankOrder and Stack Filters," Signal Processing, 38, pp. 441453, August 1994

H.R. Srinivas, B. Vinnakota, and K.K. Parhi, "A CTestable CarryFree Divider," IEEE Trans. on VLSI Systems, 2(4), pp. 472488, December 1994
1993

N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Differential Vector Quantizer for LowPower Speech Coding Applications," IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 40(5), May 1993, pp. 347349

N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Lattice Filter Architecture," IEEE Trans. on Signal Processing, 41(5), May 1993, pp. 19251939

K.J. Raghunath, and K.K. Parhi, "Parallel Adaptive Decision Feedback Equalizers," IEEE Transactions on Signal Processing, 41(5), May 1993, pp. 19561961

K.K. Parhi, and T. Nishitani, "VLSI Architectures for Discrete Wavelet Transforms," IEEE Trans. on VLSI Systems, 1(2), June 1993, pp. 191202

L.E. Lucke, and K.K. Parhi, "DataFlow Transformations for Critical Path Time Reduction For HighLevel DSP Synthesis," IEEE Transactions on Computer Aided Design of Integrated Circuits And Systems, 12(7), July 1993, pp. 10631068

N.R. Shanbhag, and K.K. Parhi, "Relaxed LookAhead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder," IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 40(12), December 1993, pp. 753766
1992

K.K. Parhi, C.Y. Wang, A.P. Brown, "Synthesis of Control Circuits in Folded Pipelined DSP Architectures," IEEE Journal of Solid State Circuits, Vol. 27, No. 1, January 1992, pp. 2943

M. Hatamian and K.K. Parhi, "An 85MHz FourthOrder Programmable IIR Digital Filter Chip," IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992, pp. 175183

H.R. Srinivas, and K.K. Parhi, "HighSpeed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation," Journal of VLSI Signal Processing, Vol. 4, No. 2/3, 1992, pp. 177198

H.R. Srinivas, and K.K. Parhi, "A Fast VLSI Adder Architecture," IEEE Journal of Solid State Circuits, Vol. 27, No. 5, May 1992, pp. 761767

K.K. Parhi, "HighSpeed VLSI Architectures for Huffman and Viterbi Decoders," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 39, No. 6, June 1992, pp. 385391

K.K. Parhi, "Video Data Format Converters Using Minimum Number of Registers," IEEE Transactions on Circuits and Systems For Video Technology, Vol. 2, No. 2, June 1992, pp. 255267

K.K. Parhi, "Systematic Synthesis of DSP Data Format Converters using LifeTime Analysis and ForwardBackward Register Allocation," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 39, No. 7, July 1992, pp. 423440
1991

K.K. Parhi, and D.G. Messerschmitt, "Static RateOptimal Scheduling of Iterative Data Flow Programs via Optimum Unfolding," IEEE Trans. on Computers, Vol. 40(2), February 1991, pp. 178195

K.K. Parhi, "A Systematic Approach for Design of DigitSerial Signal Processing Architectures," IEEE Trans. on Circuits and Systems, Vol. 38, No. 4, April 1991, pp. 358375

K.K. Parhi, "Pipelining In Dynamic Programming Architectures," IEEE Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp. 14421450

K.K. Parhi, "Finite Word Effects in Pipelined Recursive Filters," IEEE Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp. 14501454

K.K. Parhi, "Pipelining in Algorithms with Quantizer Loops," IEEE Trans. on Circuits and Systems, Vol. 38, No. 7, July 1991, pp. 745754

K.K. Parhi, "Technology for the 90s: VLSI Signal and Image Processing Systems," IEEE Circuits and Devices Magazine (special technology forecast issue), 7(4), July 1991 (invited article), pp. 1617

K.K. Parhi, "Research on VLSI For Digital Video Systems in Japan", Asian Scientific Information Bulletin of the Office of Naval Research Office, 16(4), October  December 1991, pp. 9398
1989

K.K. Parhi, and D.G. Messerschmitt, "Concurrent Architectures for TwoDimensional Recursive Digital Filtering," IEEE Trans. on Circuits and Systems, Vol. CAS36(6), June 1989, pp. 813829

K.K. Parhi, and D.G. Messerschmitt, "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part I: Pipelining using Scattered LookAhead and Decomposition," IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37(7), July 1989, pp. 10991117

K.K. Parhi, and D.G. Messerschmitt, "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering," IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37(7), July 1989, pp. 11181135

K.K. Parhi, "Algorithm Transformation Techniques for Concurrent Processors," Proceedings of the IEEE, Special Issue on Supercomputer Technology, Vol. 77(12), December 1989, pp. 18791895
1987

K.K. Parhi and D.G. Messerschmitt, "Concurrent Cellular VLSI Adaptive Filter Architectures," IEEE Transactionson Circuits and Systems, Vol. CAS34, No. 10, October 1987, pp. 11411151

K.K. Parhi and R.S. Berkowitz, "On Optimizing Importance SamplingSimulations," IEEE Transactions of Circuits and Systems, Vol. CAS34, No. 12, December 1987, pp. 15581563