Prof. Keshab K. Parhi

Edgar F. Johnson Professor of Electronic Communication
Distinguished McKnight University Professor

  • US Mail:
    Department of Electrical and Computer Engineering
    University of Minnesota
    4-174 Keller Hall
    200 Union St. S.E.
    Minneapolis, MN 55455

  • Office:
    6-181 Keller Hall

  • Telephone:
    (612) 624-4116

  • Fax:
    (612) 625-4583

  • Email:
    parhi at umn dot edu

  • Curriculum Vitae

Brief Biography

Keshab K. Parhi received the B.Tech. (Honors) degree from the Indian Institute of Technology, Kharagpur (India) in 1982 in Electrical Engineering, the M.S. degree from the University of Pennsylvania in 1984 in Electrical Engineering, and the Ph.D. degree from the University of California, Berkeley in 1988 in Electrical Engineering and Computer Sciences.

Dr. Parhi has been with the Department of Electrical & Computer Engineering at the University of Minnesota, Minneapolis, since 1988, where he was an Assistant Professor from Oct. 1988-June 1992, Associate Professor from July 1992-June 1995, and has been a Professor since July 1995. Since 2000, He has held the permanent title of "Distinguished McKnight University Professor" awarded by the Graduate School of the University. Since 1997, he has held the title of "Edgar F. Johnson Professor" awarded by the College of Science and Engineering. From July 2008 till August 2011, he served as the Director of Graduate Studies of the Electrical Engineering program. He has held short term positions in several industries such as IBM T.J. Watson Research Center (Yorktown Heights, NY), AT&T Bell Laboratories (Holmdel, NJ), NEC Corporation (Miyamae-Ku, Kawasaki, Japan), where he was a National Science Foundation Japan Fellow, Broadcom Corp., Irvine, CA, and Medtronic Corp., Minneapolis, MN. He has been a visiting Professor at Delft University (The Netherlands), Lund University (Sweden), Fudan University (Shanghai, China), and Stanford University.

Dr. Parhi is widely recognized for his work on high-level transformations of iterative data-flow computations, for developing a formal theory of computing for design of digital signal processing systems, and for contributions to multi-gigabit transceivers for wired systems such as ethernet on copper and fiber and for backplanes, and for wireless communications systems. These high-speed and low-power transceiver integrated circuit chips form the backbone of the internet. His research addresses VLSI architecture design and implementation of signal processing, communications and biomedical systems, error control coders and cryptography architectures, high-speed transceivers, stochastic computing, secure computing, and molecular/DNA computing. He is also working on intelligent classification of biomedical signals and images, for applications such as seizure prediction and detection, schizophrenia classification, biomarkers for mental disorders, brain connectivity, and screening of fundus and optical coherence tomography (OCT) images for ophthalmic abnormalities. He has published over 650 papers, is inventor or coinventor of 31 issued US Patents, has authored the text book VLSI Digital Signal Processing Systems: Design and Implementation (Wiley, 1999), and is the co-editor (with Takao Nishitani) of the reference book Digital Signal Processing for Multimedia Systems (CRC Press, March 1999). He has coauthored the research monographs Pipelined Adaptive Digital Filters (with Naresh Shanbhag, 1994), Digit-Serial Computation (with Richard Hartley, 1995) and Pipelined Lattice and Wave Digital Recursive Filters (with Jin-Gyun Chung, 1996), all published by Springer.

Dr. Parhi is the recipient of numerous awards including the 2017 Mac Van Valkenburg award from the IEEE Circuits and Systems Society, 2013 Distinguished Alumnus Award from IIT, Kharagpur, India, 2013 Graduate/Professional Teaching Award from the University of Minnesota, 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W. R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — PART I and PART II, VLSI Systems, Signal Processing, Signal Processing Letters,and Signal Processing Magazine, and served as the Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — PART I (2004-2005 term), and currently serves on the Editorial Board of the Springer Journal of Signal Processing Systems (JSPS). He has served on technical program committees of IEEE or ACM Conferences such as ASAP, ICASSP, ISCAS, HOST, Asilomar Conf. Signals, Systems and Computers, Computer Arithmetic Symp., Great Lakes Symp. on VLSI, workshop on VLSI Signal Processing, SiPS, Workshop on VLSI in Communications, and of ASP-DAC, IECS and IWISP conferences. He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996-1998, and is serving a second term currently (2019-20). He served as an elected member of the Board of Governors of the IEEE Circuits and Systems society from 2005 to 2007. He is a Fellow of IEEE (1996), the American Association for the Advancement of Science (AAAS) (2017), the Association for Computing Machinery (ACM) (2020), and the National Academy of Inventors (NAI) (2020).