Parhi Lab Alumni and Students

Current Graduate Students and Visitors

  1. Bhaskar Sen (Ph.D.)
  2. Satya Venkata Sandeep Avvaru (Ph.D.)
  3. Xingyi Liu (Ph.D.)
  4. Nanda Kumar Unnikrishnan (Ph.D.)
  5. Lulu Ge (Ph.D.)

Ph.D. Theses Supervised

  1. Lori E. Lucke, "Applying Parallel Processing Techniques to Digital Signal Processing Algorithms and Architectures for High-Level VLSI Synthesis", December 1992 (Currently Fellow, Minnetronix, St. Paul)

  2. Ching-Yi Wang, "MARS: A High-Level Synthesis Tool for Digital Signal Processing Architecture Design", December 1992, (Currently with Boston Scientific, St. Paul)

  3. Naresh R. Shanbhag, "Design of Pipelined VLSI Adaptive Digital Filters with Relaxed Look-Ahead", July 1993 (Currently Jack Kilby Professor of ECE at Univ. of Illinois , Urbana)

  4. H.R. Srinivas, "Floating Point Computer Arithmetic Architectures", September 1994, (Currently with Broadcom, Irvine, CA)

  5. Raghu Kalavai, "Pipelined STAR RLS Adaptive Filters", October 1994, (Currently with Ikanos, NJ)

  6. Jin-Gyun Chung, "Pipelined IIR Lattice and Wave Digital Filters", November 1994, (Currently Dean of Engineering at Chonbuk National University , Chonju, S. Korea)

  7. Tracy C. Denk, "Retiming, Folding and Register Minimization", July 1996, (Currently with Newport Media Inc. , Irvine, CA)

  8. Janardhan H. Satyanarayana, "Design of Low-Power DSP Systems", March 1998, (Currently with Intel , Austin, TX)

  9. Ahmed Shalash, "Architecture and System Design for Digital Subscriber Loop Communications", June 1998, (Currently Professor at Cairo University , Egypt)

  10. Leilei Song, " Low-Power VLSI Architectures for Finite-Field Applications", June 1999, (Currently at Intel, Santa Clara, CA)

  11. Yun-Nan Chang, "Low-Power Bit-Serial and Digit-Serial DSP Systems", June 1999, (Currently Professor at National Sun Yat-Sen University, Kaohsiung, Taiwan)

  12. Jun Ma, "Pipelined RLS Adaptive Filters", July 1999, (Currently Professor at Jiao Tong University, Shanghai, China)

  13. Martin Kuhlmann, "High-Performance Low-Power Arithmetic Architectures and Circuits", Dec. 1999

  14. Vijay Sundararajan, "Performance Optimization Methodologies for Design of Digital VLSI Systems", Jan. 2000 (Currently Assoc. Technical Director at Broadcom, San Jose)

  15. Zhongfeng Wang, "High-Performance and Low-Cost VLSI Design of Turbo Decoders", Aug. 2000, (Currently Professor at Nanjing University, Nanjing, China)

  16. Robert A. Freking, "Structural Strategies for High-Performance Undelimited-Codeword Source Coding", Oct. 2000, (Currently with M.I.T. Lincoln Laboratories, MA)

  17. William L. Freking, "Algorithms and Architectures for High-Performance Public-Key Cryptosystems", October 2000 (Currently with M.I.T. Lincoln Laboratories, MA)

  18. Lijun Gao, "Architecture Design and Mapping of DSP Systems", Feb. 2001, (Currently with Analog Devices, Boston, MA]

  19. Zhipei Chi, "High-Performance, High-Speed VLSI Architectures for Wireless Communications Applications", June 2001, (Currently with Marvell Technology Group, Calif.)

  20. Tong Zhang, "Efficient VLSI Architectures for Error-Correction Coding", June 2002, (Currently Professor, Dept. ECSE, RPI, Troy, NY)

  21. Yanni Chen, " Low-Complexity High-Speed VLSI Architectures for Error-Correction Decoders", May 2003, (Currently Apple, Cupertino, CA)

  22. Jun Jin Kong, "Classical and Quantum Convolutional Codes: Design and Implementation", Feb. 2005, (Currently "Master" at Samsung, South Korea)

  23. Xinmiao Zhang, "Architectures for Error Control Coders and Cryptography Systems", June 2005, (Currently Associate Professor at Ohio State University)

  24. Yongru Gu, "VLSI Architectures for High-Speed Transceivers", July 2005, (Currently at InPlay Technology, Irvine, CA)

  25. Jun Tang, "Architectures for OFDM Based Ultra Wideband Systems", August 2006, (Currently at InPlay Technology, Irvine, CA)

  26. Sang-Min Kim, "Efficient VLSI Architectures for Error Control Coders", October 2006, (Currently with Qualcomm, San Diego, CA)

  27. Jian-Hung Lin, "Algorithms and Architectures for Next Generation Multimedia Communications Systems", January 2007, (Currently with MaxLinear , Irvine, CA)

  28. Yuping Zhang, "VLSI Architectures for Turbo Code Decoder, LDPC Code Decoder and List Sphere Decoder", May 2007, (Currently with Apple, CA)

  29. Chao Cheng, "High-Speed Low-Cost VLSI DSP Algorithms Based on Novel Fast Convolutions and Look-Ahead Pipelining Structures" May 2007, (Currently with Qualcomm, Santa Clara, CA)

  30. Aaron E. Cohen, "Architectures for Cryptography Accelerators", September 2007, (Currently with Naval Research Lab, Washington, DC)

  31. Daesun Oh, "Low Complexity VLSI Architectures for LDPC Decoders", May 2008 (Currently with Samsung, South Korea)

  32. Jie Chen, "Efficient VLSI Architectures for High-Speed Ethernet Transceivers", Aug. 2008 (Currently Manager at Marvell Technology Group, Santa Clara, CA)

  33. Renfei Liu, "Error Control Algorithms and Architectures for Reliable DSP Systems," Nov. 2010 (Currently with Broadcom Corp., Irvine, CA)

  34. Yun Sang Park, "Reduced-Complexity Epileptic Seizure Prediction with EEG," Jan. 2012 (Coadvised by Prof. Theoden I. Netoff) (Currently with Samsung, S. Korea)

  35. Hua Jiang, "Digital Logic and Signal Processing Computations with Molecular Reactions," May 2012 (Coadvised by Prof. Marc D. Riedel) (Currently with Netflix, CA)

  36. Manohar Ayinala, "Low-Power Architectures for Signal Processing and Classification Systems," July 2012 (Currently with Intel, Allentown, PA)

  37. Chuan Zhang, "Low-Latency Low-Complexity Channel Decoder Architectures for Modern Communication Systems," December 2012 (Currently Associate Professor at Southeast University, China)

  38. Te-Lung Kung, "Synchronization and Coding in Wireless Communication Systems," September 2013

  39. Sohini Roychowdhury, "Automated Segmentation and Pathology Detection in Ophthalmic Images," July 2014 (Currently with Volvo, Mountain View, CA)

  40. Yingjie Lao, "Authentication and Obfuscation of Digital Signal Processing Integrated Circuits," July 2015 (Currently Assistant Professor at Clemson University, South Carolina)

  41. Bo Yuan, "Algorithm and VLSI Architecture for Polar Codes Decoder," July 2015 (Currently Assistant Professor at Rutgers University)

  42. Tingting Xu, "Biomarkers for Mental Disorders from Neuroimaging Data," December 2016 (Ad Colony, Seattle)

  43. Yin Liu, "Digital Signal Processing and Machine Learning System Design using Stochastic Logic," July 2017 (Microsoft, Redmond, WA)

  44. Sayed Ahmad Salehi, "A Framework for Computing Discrete-Time Systems and Functions using DNA," July 2017, (Coadvised by Prof. Marc D. Riedel) (Assistant Professor, University of Kentucky)

  45. Zisheng Zhang, "Approaches to Feature Identification and Feature Selection for Binary and Multi-Class Classification," July 2017 (irhythm, San Francisco)

  46. Sandhya Koteshwara, "Secure, Resilient and Low-Energy Hardware Architectures for Internet-of-Things," September 2018 (IBM T.J. Watson Research Center, Yorktown Heights, New York)

  47. Shu-Hsien Chu, "Approaches to Anatomical and Functional Brain Connectivity Analysis with Applications to Adolescent Major Depressive Disorder," September 2018, (Coadvised by Prof. Christophe Lenglet) (Intel, Oregon)

M.S. Projects/Theses Supervised

  1. Gregory S. Munson, "Finite Precision Effects in Scattered and Clustered Look-Ahead Pipelined Recursive Digital Filter Implementations," June 1989,

  2. Jim Malaney , "Design of a Programmable Digital Filter," November 1989

  3. Lai Q. Pham , "Roundoff Errors in Digital Filters using Redundant Numbers," November 1989

  4. Syed Babar Raza , "Reduction of Hardware Overhead in Recursive Filters by Interleaving," January 1991

  5. Joo-Sang Lee , "A New Approach for Design of Data Format Converter Architectures using Register Allocation," May 1991

  6. H.R. Srinivas, "High-Speed VLSI Arithmetic Processor Architectures using Hybrid Number Representation," July 1991

  7. N. Iyer , "iSchematic: An Automatic Schematic Generator for OCT 5.0 Database," September 1991

  8. Andrew P. Brown, "Applications of Circuit Retiming to DSP Architecture Design," October 1991

  9. Jin-Gyun Chung, "Synthesis of Pipelined Lattice IIR Digital Filter," November 1991

  10. Gireesh Shrimali, "Fast Arithmetic Coder Architectures," June 1993

  11. Wayne C. Amendola, Jr., "VLSI Implementation of a 200 MHz 16x16 Redundant Digit Multiplier and a 125 MHz Booth-Encoded Redundant Digit Multiplier," June 1993

  12. Bin Fu, "VLSI Design Advances in Arithmetic Coding," May 1995

  13. Santosh Mishra, "CDMA Based Mobile Communications Systems," May 1995

  14. Darren Pearson, "Low Power Strategies for VLSI Implementation of Digital Filters," May 1995

  15. Surendra Jain, "Efficient VLSI Architectures for Finite Field Arithmetic," June 1995

  16. Yun-Nan Chang, "High-Level DSP Synthesis using Heterogeneous Functional Units," June 1995

  17. Yuet Li, "STAR ADaptive Lattice Recursive Least Square Filters," Feb. 1996

  18. Chong Xu, "Power-Speed Reconfigurable FIR Filters," Feb. 1996

  19. David Parker, "Low-Area/Power Parallel FIR Filters," May 1996

  20. Mayukh Majumdar, "Low-Area Data Format Converters," June 1996

  21. Leilei Song, "Efficient Bit-Serial Finite Field Multipliers," June 1996

  22. John Bratt, "Low-Area Data Format Converters,"VHDL Interface for MARS DSP Synthesis System," June 1996

  23. Hojun Kim, "Coefficient Optimization in Pipelined IIR Digital Filters," July 1996

  24. Mousumi Gayen, "ILP Scheduling with Processor Interconnection," Jan. 1997

  25. Nikhil Sarpotdar, "Radix-2 Division and Square-Root Algorithms: Study and Implementation," July 1997

  26. William Ho , "Power Efficiency of the Carry-Select Adder," Aug. 1997

  27. Ashish Karandikar, "Low-Power and High-Performance Static Random Access Memory," Dec. 1997

  28. Zhipei Chi , "Pipelined Single-Channel and Multi-Channel Lattice RLS Adaptive Filters," Sept. 1998

  29. Nidish Kamath, "Scheduling DSP Algorithms for Low-Power Design," Jan. 1999

  30. Dhiraj Kumar, "Performance Tradeoffs of DCT Architectures in Xilinx FPGAs," April 1999

  31. Ziyu Li, "DLMS Adaptive Filter: Bit-Serial Systolic Array VLSI Implementation," July 1999

  32. Robin Bansal, "Optimized Power and Delay Solutions for Digital CMOS Circuits by Transistor Reordering using HEAT," August 1999

  33. Ru-Guang Chen, "Double error Correction on Residue Number System," Feb. 2000

  34. Bibhudatta Sahoo, "A Low-Power Correlator," Aug. 2000

  35. Siwei Chen, "Minimum Switching Activity Schedules for Various FIR Filters," Aug. 2000

  36. Wenhao Wu, "VLSI Design and Implementation of Two viterbi Decoders," Aug. 2000

  37. Karuna Prasad, "Power Analysis of 4-2 and 5-2 Compressors," Jan. 2001

  38. Aaron E. Cohen, "VLSI Architectures for RSA," June 2004

  39. Saurabh Jain, "Low-Complexity Pipelined-Parallel Decision feedback Decoder (PDFD) for 1 Gbps ethernet," Aug. 2004

  40. Lina Long, "A VLSI Implementation for Viterbi Decoder in Ultra-Wideband System," March 2005

  41. Manoj Yadav, "LDPC Decoder for DVB System," May 2005

  42. Renfei Liu , "VLSI Architectures for Viterbi Decoders," May 2007

  43. Daesun Oh , "LDPC Decoder Architectures," Feb. 2008

  44. Jie Chen , "Architectures for 10-gigabit Ethernet," Feb. 2008

  45. Priyadharshini Vijayakumar , "Timing Variations in Digital Filters with Supply Variations," August 2008

  46. Prashant Metkar , "Improved Approach for Calculating Model Parameters in Speaker Recognition using Gaussian Mixture Models," May 2009

  47. Jaime Rivera, "Research for the Development of an Apparatus to help Prevent Sudden Infant Death," May 2009

  48. Xiaoming Zhu, "Lung Sound separation by Independent Component Analysis," June 2009

  49. Yun-Sang Park, "Seizure Prediction by Support Vector Ma chine Classification," Jan. 2010

  50. Yingbo Hu, "Subthreshold Circuit Design," August 2010

  51. Manohar Ayinala, " High-Throughput VLSI Architectures for CRC/BCH Encoders and FFT Computations," Nov. 2010

  52. Lan Luo, "Postprocessing of Seizure Prediction by Kalman Filter," May 2011

  53. Te-Lung Kung, "Frame Start Synchronization in OFDM System," September 2011

  54. Michael Brown, "A Low-Complexity Seizure Prediction Algorithm," November 2011

  55. Chuan Zhang, "Polar Code Decoder Architectures," April 2012

  56. Tingting Xu, "Schizophrenia Classification from MEG," April 2012

  57. Manikandan Palani , "EEG Data Compression," May 2014

  58. Aravinth Chinnapalanichamy , "Serial and Interleaved FFT Architectures for Real Signals," Jan. 2015

  59. Sandhya Koteswara, "Obfuscated FFT Architecture," Feb. 2015

  60. Sayed Ahmad Salehi, "DNA Computing," April 2015

  61. Yingjie Lao, "Removing Redundancies of Fast Fourier Transform Computations," July 2015

  62. Goutham N.C. Shangumam, "An obfuscated radix-2 real FFT architecture," Sept. 2015

  63. Vaishnavi Santhapuram, "Timing Induced Error Analysis for Wallace Tree Multipliers," Oct. 2015

  64. Anoop Koyily, "A Study on Modeling of MUX-based Physical Unclonable Functions," April 2018

Former Visitors

  1. Dr. Kazuhito Ito (1992-1993)

  2. Dr. Ching-Yi Wang (1993-1996)

  3. Dr. Luis Montalvo (1995-1996)

  4. Prof. Michalis Zervakis (1996)

  5. Dr. Steve Summerfield (1997)

  6. Mr. Hiroshi Suzuki (1997-1999)

  7. Dr. Javier Valls (1999)

  8. Dr. Trini Sansaloni (1999)

  9. Dr. Yuke Wang (1999)

  10. Dr. Jin-Gyun Chung (2001)

  11. Dr. Chester (Sungchung) Park (2005)

  12. Ms. Chunlei Xia (2006)

  13. Dr. Mario Garrido (2007)

  14. Dr. Hemant Patil (2009)

  15. Dr. Xiaoping Li (2010)

  16. Sayed Ahmad Salehi, (Predoctoral Visitor from Isfahan Univ., Iran) (2011-12)

  17. Mojtaba Bandarabadi (Predoctoral Visitor from Coimbra University, Portugal) (Coadvised by Prof. Tay Netoff) (2012)

  18. Prof. Yun-Nan Chang (Visiting Professor from National Sun Yat-Sen Univ., Taiwan) (2012)

  19. Abdolreza Rashno (Pre-Doctoral Visitor from Isfahan University of Technology, Iran) (2016)

Recent Senior Design Students

Spring 2018

Project: Physical Unclonable Functions

Group Photo

  1. Alex Ayling
  2. Peyton Bechhold
  3. William Fox
  4. Moudu Jaw
  5. Sung Won Kang
  6. Michael Ziebarth

Spring 2016

Project: Segmentation of Electrocardiogram

Coadvisor: Cathie Condie, Medtronic

Group Photo

  1. Alex Motley
  2. Blake Trantina
  3. Emily Mattison
  4. Jahanara Ahsan
  5. Tikuabo Atsbaha

Spring 2015

Project: Web App Design for Vessel Segmentation of Fundus Images

  1. Peter Brudzinski
  2. Shilin Chen
  3. Tom Hinrichs
  4. VĂ­tor Matos
  5. Yingnan Wang

Fall 2013

Project: Web App Design for Vessel Segmentation of Fundus Images

  1. Nathan Bruner
  2. Smitesh Kharat
  3. Tyler Krause-Lewis
  4. Niraj Rayalla
  5. Hassan Saleh
  6. Lucas Sherman

Spring 2012

Project: Simultaneous Audio Recording Interface

Coadvisor: Michael Brown

  1. Debbie Baran
  2. Calvin Behling
  3. Dale Frolik
  4. Micah Hakala
  5. Nick Mensen
  6. Ben Wilde

Fall 2009

Project: Breaker Controller and Waveform Generator Test-Set FPGA Project

Coadvisor: Joe Ruether, Xcel Energy

  1. Nate Bolyard
  2. Hugo Guadalupe Chavolla
  3. Justin Thomas Fuith
  4. Brandon Joshua Rice
  5. Elsayed G Shamekh

Fall 2003

  1. Arash Allaei
  2. Spencer Dille
  3. Erik Freed
  4. Minassie Tewoldebrhan
  5. Matthew Russell

Group Photos

2003

2004

2005

2006

2007

2012

2013

2017

April

ISCAS (May)

China (June)