TCAD Best Paper Award

The Donald O. Pederson Award recognizes the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in the two calendar years preceding the award. Any paper published in the Transactions during this period may be nominated for the award. Various factors are taken into account while judging the nominees, including the overall quality, the originality, the level of contribution, the subject matter, and the timeliness of the research.

Past Winners of the TCAD Best Paper Award

Year Awarded	Award Winner
2011	Amith Singhee and Rob A. Rutenbar, " Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design”," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 8, pp. 1176-1189, August 2009.
2010	Chris Chu and Yiu-Chung Wong, “FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 70-83, January 2008.
2009	Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, “Systematic and Automated Multiprocessor System Design, Programming, and Implementation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 542-555, March 2008.
2008	Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert K. Brayton, and Malgorzata Chrzanowska-Jeske, “Using simulation and satisfiability to compute flexibilities in Boolean networks”, vol. 25, no. 5, pp. 743-755, May 2006.
2007	Guoyong Shi, Bo Hu, and C.-J. Richard Shi, “On Symbolic Model Order Reduction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2007.
2006	Mark Kassab, Janusz Rajski, Jerzy Tyszer, and Nilanjan Mukherjee, “Embedded Deterministic Test”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 23, no. 5, pp. 776-792, May 2006.
2005	Subhasish Mitra and Kee Sup-Kim, “X-compact: An Efficient Response Compaction Technique”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 421-432 March 2004.
2004	Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes, “Synthesis of Reversible Logic Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710-722, June 2003.
2003	Yirng-An Chen and Randal E. Bryant, “An Efficient Graph Representation for Arithmetic Circuit Verification”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1443-1454, December 2001.
2002	Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, and Takeshi Yoshimura, “Floorplanning Using a Tree Representation”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pg. 281-289, February 2001.
2001	Shigeru Yamashita, Hiroshi Sawada, and Akira Nagoya, “SPFD: A New Method to Express Functional Flexibility”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 840-849, August 2000.
2000	Chris C.N. Chu and Martin D.F.Wong, “A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 787-798, June 1999.
1999	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 645-654, August 1998.

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