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*Selected Research Highlights of Keshab K. Parhi
*

##
Theory of DSP Architectures/High Level Architecture Synthesis

First Formulation of Algorithm Transformations for DSP Computing
(Proc. IEEE, Dec. 1989)
First Formulation and introduction of the * folding algorithm * to synthesize
time-multiplexed DSP circuits from data-flow graphs for specified folding sets
(IEEE JSSC, Jan. 1992)
First Formulation and introduction of the * unfolding algorithm * to unfold or unroll
digital signal processing data-flow graphs
(IEEE Trans. Computers, Feb. 1991)
First formulation of retiming and folding for multi-rate digital signal processing data-flow graphs
(IEEE T-VLSI, Dec. 1998)
Retiming for two-dimensional DSP data-flow graphs
(IEEE T-VLSI, June 1999)
First exhaustive generation of all retiming and scheduling solutions for digital signal processing data-flow graphs
(IEEE T-CAS-II, July 1998)
Loop scheduling algorithms and the MARS DSP Synthesis Tool
(IEEE T-CAD, March 1995)
HEAT tool for Power estimation in DSP Systems
(IEEE D&T Magazine, April 2000)
A maximum cycle mean algorithm for computing iteration period bound of DSP data-flow graphs
(Springer JSPS, Dec. 1995)
##
Pipelining, Parallel Processing, and Arbitrary Concurrency

First pipelining of IIR digital filters using * scattered look-ahead transformation *
(IEEE T-ASSP, Part-I, July 1989)
First combined pipelining and parallel processing of IIR digital filters
(IEEE T-ASSP, Part-II, July 1989)
First approach to pipelining quantizer loop based DSP algorithms
using parallel-branch and delayed-decision techniques
(IEEE T-CAS, July 1991)
First pipelining of lattice IIR Digital filters
(IEEE T-SP, April 1994)
First formulation of * relaxed look-ahead transformation *
for pipelining the LMS Adaptive filter
(IEEE T-CAS-II, Dec. 1993)
First pipelining of the QRD-RLS Adaptive filter using
* annihilation reordering * transformation
(IEEE T-SP, Aug. 2000)
First pipelining and parallel processing of the Tomlinson-Harashima precoder
(IEEE T-CAS-I, Sept. 2007)
(
IEEE T-CAS-II, May 2008)
Arbitrary concurrency in Huffman decoders
(IEEE ICASSP 1999)
Arbitrary concurrency in Arithmetic coders
(IEEE T-SP, Oct. 2006)
Arbitrary concurrency in CRC checks, BCH encoders, and linear feedback shift registers
(IEEE T-SP, Sept. 2011)
##
VLSI Signal Processing Architectures

An architecture for discrete wavelet transform
(IEEE T-VLSI, June 1993)
First optimization of FFT architectures for real input signals
(IEEE T-CAS-I, Dec. 2009)
Generalized FFT Architectures using Folding
(IEEE T-VLSI, June 2012)
Low-Energy Architectures for Welch Power Spectral Density
(IEEE T-CAS-I, Jan. 2014)
First architectures for multi-gigabit decision feedback equalizers
(IEEE T-VLSI, April 2005)
Pipelined parallel decision feedback decoder
(IEEE T-SP, Feb. 2007)
Complexity reduction in parallel FIR filter
(Springer September 1997)
(IEEE T-CAS-I, Aug. 2004)
FEXT cancellation and equallization for 10-gigabit ethernet
(IEEE T-CAS-I, June 2009)
##
VLSI Error Control Code Decoder Architectures

Architectures for arbitrarily parallel turbo decoders
(IEEE T-VLSI, Dec. 2002)
Joint (3,k) low-density parity check code/decoder
(IEEE T-SP, April 2004)
First parallel Viterbi decoder with logarithmic latency with respect to parallelism
(IEEE T-VLSI, June 2004)
New Retiming in Add-Compare-Select Loop of Viterbi Decoder
(IEEE Trans. Circuits and Systems-I, March 2004)
Fast factorization in soft-decision Reed-Solomon decoder
(IEEE T-VLSI, April 2005)
(IEEE T-CAS-I, June 2009)
Low-Latency Polar Code Decoder Architectures
(IEEE T-SP, June 2013)
(IEEE T-CAS-I, April 2014)
(IEEE TVLSI, Oct. 2015)
##
Binary/Finite Field Arithmetic, Cryptography, and Hardware Security

A new low-power binary adder
(IEEE T-VLSI, Dec. 1999)
Systolic architectures for modular multiplication
(Springer JSPS, April 2002)
High-speed architectures for the AES algorithm
(IEEE T-VLSI, Sept. 2004)
High-speed architectures for elliptic curve cryptography
(Springer JSPS, July 2010)
Performance Analysis of MUX Physical Unclonable Functions
(IEEE T-CAD, 2014)
Obfuscated DSP Circuits that are harder to reverse engineer
(IEEE T-VLSI, May 2015)
True Random Number Generators
(ACM JETC, April 2016)
##
Brain/Biomedical Signal Classification, and Machine Learning

Prediction of Seizures in Epileptic Patients
(Epilepsia, Oct. 2011)
(IEEE TBCAS, 2016)
Brain Connectivity based Classification in Borderline Personality Disorder
(NeuroImage: Clinical, 2016)
Schizophrenia Identification from MEG
(IEEE TNSRE, 2016)
Diabetic Retinopathy Screening using DREAM tool
(IEEE JBHI, 2014)
##
Molecular Signal Processing/DNA Computing

Molecular Computing and Sensing Systems
(IEEE Trans. Molecular, Biological, and Multiscale Communications, Sept. 2015)
First Discrete-Time Signal Processing using Molecular Reactions/DNA Strands
(IEEE Design & Test, May/June 2012) and
(ACS Synthtic Biology, 2013)
Computing Polynomials using DNA
(ACS Synthetic Biology, Jan. 2017)
Synchronous Sequential Computation with Molecular Reactions/DNA Strands
(IEEE DAC-2011) and
(IEEE ICCAD-2013)
*
[Prof.
Parhi's homepage]
*