Ph.D. Theses Supervised by Keshab K. Parhi:

  1. Lori E. Lucke, "Applying Parallel Processing Techniques to Digital Signal Processing Algorithms and Architectures for High-Level VLSI Synthesis", December 1992 (Currently Fellow, Minnetronix, St. Paul)
  2. Ching-Yi Wang, "MARS: A High-Level Synthesis Tool for Digital Signal Processing Architecture Design", December 1992, (Currently with Boston Scientific, St. Paul)
  3. Naresh R. Shanbhag, "Design of Pipelined VLSI Adaptive Digital Filters with Relaxed Look-Ahead", July 1993 (Currently Jack Kilby Professor of ECE at Univ. of Illinois , Urbana)
  4. H.R. Srinivas, "Floating Point Computer Arithmetic Architectures", September 1994, (Currently with Broadcom, Irvine, CA)
  5. Raghu Kalavai, "Pipelined STAR RLS Adaptive Filters", October 1994, (Currently with Ikanos, NJ)
  6. Jin-Gyun Chung, "Pipelined IIR Lattice and Wave Digital Filters", November 1994, (Currently Dean of Engineering at Chonbuk National University , Chonju, S. Korea)
  7. Tracy C. Denk, "Retiming, Folding and Register Minimization", July 1996, (Currently with Newport Media Inc. , Irvine, CA)
  8. Janardhan H. Satyanarayana, "Design of Low-Power DSP Systems", March 1998, (Currently with Intel , Austin, TX)
  9. Ahmed Shalash, "Architecture and System Design for Digital Subscriber Loop Communications", June 1998, (Currently Professor at Cairo University , Egypt)
  10. Leilei Song, " Low-Power VLSI Architectures for Finite-Field Applications", June 1999, (Currently at Intel, Santa Clara, CA)
  11. Yun-Nan Chang, "Low-Power Bit-Serial and Digit-Serial DSP Systems", June 1999, (Currently Professor at National Sun Yat-Sen University, Kaohsiung, Taiwan)
  12. Jun Ma, "Pipelined RLS Adaptive Filters", July 1999, (Currently Professor at Jiao Tong University, Shanghai, China)
  13. Martin Kuhlmann, "High-Performance Low-Power Arithmetic Architectures and Circuits", Dec. 1999
  14. Vijay Sundararajan, "Performance Optimization Methodologies for Design of Digital VLSI Systems", Jan. 2000 (Currently Assoc. Technical Director at Broadcom, San Jose)
  15. Zhongfeng Wang, "High-Performance and Low-Cost VLSI Design of Turbo Decoders", Aug. 2000, (Currently Professor at Nanjing University, Nanjing, China)
  16. Robert A. Freking, "Structural Strategies for High-Performance Undelimited-Codeword Source Coding", Oct. 2000, (Currently with M.I.T. Lincoln Laboratories, MA)
  17. William L. Freking, "Algorithms and Architectures for High-Performance Public-Key Cryptosystems", October 2000 (Currently with M.I.T. Lincoln Laboratories, MA)
  18. Lijun Gao, "Architecture Design and Mapping of DSP Systems", Feb. 2001, (Currently with Analog Devices, Boston, MA]
  19. Zhipei Chi, "High-Performance, High-Speed VLSI Architectures for Wireless Communications Applications", June 2001, (Currently with Marvell Technology Group, Calif.)
  20. Tong Zhang, "Efficient VLSI Architectures for Error-Correction Coding", June 2002, (Currently Professor, Dept. ECSE, RPI, Troy, NY)
  21. Yanni Chen, " Low-Complexity High-Speed VLSI Architectures for Error-Correction Decoders", May 2003, (Currently Apple, Cupertino, CA)
  22. Jun Jin Kong, "Classical and Quantum Convolutional Codes: Design and Implementation", Feb. 2005, (Currently "Master" at Samsung, South Korea)
  23. Xinmiao Zhang, "Architectures for Error Control Coders and Cryptography Systems", June 2005, (Currently Associate Professor at Ohio State University)
  24. Yongru Gu, "VLSI Architectures for High-Speed Transceivers", July 2005, (Currently at InPlay Technology, Irvine, CA)
  25. Jun Tang, "Architectures for OFDM Based Ultra Wideband Systems", August 2006, (Currently at InPlay Technology, Irvine, CA)
  26. Sang-Min Kim, "Efficient VLSI Architectures for Error Control Coders", October 2006, (Currently with Qualcomm, San Diego, CA)
  27. Jian-Hung Lin, "Algorithms and Architectures for Next Generation Multimedia Communications Systems", January 2007, (Currently with MaxLinear , Irvine, CA)
  28. Yuping Zhang, "VLSI Architectures for Turbo Code Decoder, LDPC Code Decoder and List Sphere Decoder", May 2007, (Currently with Apple, CA)
  29. Chao Cheng, "High-Speed Low-Cost VLSI DSP Algorithms Based on Novel Fast Convolutions and Look-Ahead Pipelining Structures" May 2007, (Currently with Qualcomm, Santa Clara, CA)
  30. Aaron E. Cohen, "Architectures for Cryptography Accelerators", September 2007, (Currently with Naval Research Lab, Washington, DC)
  31. Daesun Oh, "Low Complexity VLSI Architectures for LDPC Decoders", May 2008 (Currently with Samsung, South Korea)
  32. Jie Chen, "Efficient VLSI Architectures for High-Speed Ethernet Transceivers", Aug. 2008 (Currently Manager at Marvell Technology Group, Santa Clara, CA)
  33. Renfei Liu, "Error Control Algorithms and Architectures for Reliable DSP Systems," Nov. 2010 (Currently with Broadcom Corp., Irvine, CA)
  34. Yun Sang Park, "Reduced-Complexity Epileptic Seizure Prediction with EEG," Jan. 2012 (Coadvised by Prof. Theoden I. Netoff) (Currently with Samsung, S. Korea)
  35. Hua Jiang, "Digital Logic and Signal Processing Computations with Molecular Reactions," May 2012 (Coadvised by Prof. Marc D. Riedel) (Currently with Netflix, CA)
  36. Manohar Ayinala, "Low-Power Architectures for Signal Processing and Classification Systems," July 2012 (Currently with Intel, Allentown, PA)
  37. Chuan Zhang, "Low-Latency Low-Complexity Channel Decoder Architectures for Modern Communication Systems," December 2012 (Currently Associate Professor at Southeast University, China)
  38. Te-Lung Kung, "Synchronization and Coding in Wireless Communication Systems," September 2013
  39. Sohini Roychowdhury, "Automated Segmentation and Pathology Detection in Ophthalmic Images," July 2014 (Currently with Volvo, Mountain View, CA)
  40. Yingjie Lao, "Authentication and Obfuscation of Digital Signal Processing Integrated Circuits," July 2015 (Currently Assistant Professor at Clemson University, South Carolina)
  41. Bo Yuan, "Algorithm and VLSI Architecture for Polar Codes Decoder," July 2015 (Currently Assistant Professor at City University of New York)
  42. Tingting Xu, "Biomarkers for Mental Disorders from Neuroimaging Data," December 2016 (Ad Colony, Seattle)
  43. Yin Liu, "Digital Signal Processing and Machine Learning System Design using Stochastic Logic," July 2017 (Microsoft, Redmond, WA)
  44. Sayed Ahmad Salehi, "A Framework for Computing Discrete-Time Systems and Functions using DNA," July 2017, (Coadvised by Prof. Marc D. Riedel) (Utah Valley University)
  45. Zisheng Zhang, "Approaches to Feature Identification and Feature Selection for Binary and Multi-Class Classification," July 2017 (irhythm, San Francisco)

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