Kia's Publications

Book Chapters

  • Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, "Synthesizing combinational logic to generate probabilities: theories and algorithms," in Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati editors, Springer Publishing, 2011.

  • Kia Bazargan, "Chapter 10.2: FPGA Technology Mapping, Placement, and Routing", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press

  • Sachin Sapatnekar, Kia Bazargan, "Chapter 10.4: 3D Design", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press.

Journal Papers

  • M. Hassan Najafi, David Lilja, Marc Riedel, and Kia Bazargan, "Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits", IEEE Transactions on Computers, 2017.

  • M. Hassan Najafi, P. Li, D. J. Lilja, W. Qian, K. Bazargan, M. Riedel, "A Reconfigurable Architecture with Sequential Logic-based Stochastic Computing," ACM Journal on Emerging Technologies in Computing Systems, 2017.

  • M. Hassan Najafi, S Jamali-Zavareh, D. J. Lilja, M. Riedel, K. Bazargan, and R. Harjani, "Time-Encoded Values for Highly Efficient Stochastic Circuits," IEEE Transaction on Very Large Scale Integration Systems, 2017.

  • Zhiheng Wang, Ryan Goh, Kia Bazargan, Arnd Scheel, and Naman Saraf, "Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map" , in IEEE Transactions on VLSI (TVLSI), 2016.

  • Divya Mahajan, Kartik Ramkrishnan, Rudra Jariwala, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Anandhavel Nagendrakumar, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan, "AXILOG: Abstractions for Approximate Hardware Design and Reuse" , in IEEE Micro, Vol 35, No 5, pp. 16-30, 2015.

  • Peng Li, David Lilja, Weikang Qian, Kia Bazargan, and Marc D. Riedel, "Computation on Stochastic Bit Streams Digital Image Processing Case Studies" , in IEEE Transactions on VLSI Systems, Vol 22, No 3, pp. 449-462, 2014.

  • Peng Li, David Lilja, Weikang Qian, Marc D. Riedel, Kia Bazargan, "Logical Computation on Stochastic Bit Streams with Linear Finite State Machines" , in IEEE Transactions on Computers, Vol. 63, No. 6, pp. 1473-1485, June 2014.

  • Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, and David J. Lilja, "An architecture for fault-tolerant computation with stochastic logic," in IEEE Transactions on Computers, vol. 60, no. 1, pp. 93-105, 2011.

  • Pongstorn Maidee and Kia Bazargan, "Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29 (12), pp. 1870 – 1883, 2010.

  • Hushrav D Mogal, Haifeng Qian, Sachin S Sapatnekar and Kia Bazargan, "Fast and Accurate Statistical Criticality Computation under Process Variations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 28 (3): 350-363, 2009.

  • Satish Sivaswamy and Kia Bazargan, "Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs", ACM Transactions on Reconfigurable Technology and Systems, Vol 1, No 1, pp. 1-35, Mar 2008.

  • Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner and Eli Bozorgzadeh, "Statistical Analysis and Design of HARP Routing Pattern FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2088-2102, Vol. 25, No. 10, October 2006.

  • Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, and Sachin S. Sapatnekar, "Placement and Routing in 3D Integrated Circuits", IEEE Design and Test, Vol. 22, No. 6, pp. 520-531, Nov-Dec 2005.

  • Ying Chen, Karthik Ranganathan, Vasudev V Pai, David J. Lilja, and Kia Bazargan, "A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory", Journal of Computer Science and Technology (JCST), 2005.

  • Cristinel Ababei, Hushrav Mogal, and Kia Bazargan, "Three-dimensional Place and Route for FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, Issue 6, pp. 1132-1140, June 2006.

  • C. Ababei and Kia Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics", International Journal of Embedded Systems (IJES) - esp. issue on Reconfigurable Architectures Workshop (RAW), Issue 1/2, Inderscience Publishers, pp. 86-94, 2006.

  • Pongstorn Maidee, Cristinel Ababei, and Kia Bazargan, "Timing-driven Partitioning-based Placement for Island Style FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 3, pp. 395 - 406, Mar. 2005.

  • Jinghuan Chen, Jaekyun Moon, and Kia Bazargan, "FPGA-based Reconfigurable Generation of Readback Signals", IEEE Transaction on Magnetics, Vol. 4, No. 3, pp. 1744 - 1750, May 2004.

  • A. Ranjan, Kia Bazargan, S. Ogrenci and M. Sarrafzadeh, "Fast Floorplanning for Effective Prediction and Construction", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, Issue 2, pp. 341-351, April 2001.

  • Kia Bazargan, R. Kastner and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems", Design Automation for Embedded Systems (DAfES) - RSP'99 Special Issue, April 2000.

  • Kia Bazargan, R. Kastner and M. Sarrafzadeh, "Fast Template Placement for Reconfigurable Computing Systems", IEEE Design and Test - Special Issue on Reconfigurable Computing, pp. 68-83, Volume 17 , Issue 1, January, 2000.

  • Kia Bazargan, S. Kim and M. Sarrafzadeh, "Nostradamus: A Floorplanner of Uncertain Designs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 18, No. 4, pp. 389-397, April 1999.

Conference Papers

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