From NCSU EDA Wiki

Metal Layers

Name	Pitch (Width/Space) (nm)	Thickness (nm) (1)	Resistivity (ohm/sq)	Permittivity	Via dimension (nm)	via resistance (ohm) (2)
ILD 9		2000		2.5	800	0.5
Global(9-10)	1600 (800/800)	2000	0.030 (3)	2.5
ILD 7-8		820		2.5	400	1
ThinGlobal (7-8)	800 (400/400)	800	0.075 (3)	2.5
ILD 4-6		290		2.5	140	3
Semi-global	280 (140/140)	280	0.21	2.5
ILD 2-3		120		2.5	70	5
Intermediate (2-3)	140 (70/70)	140	0.25	2.5
ILD 1		120		2.5	65	6
Metal 1	130 (65/65)	130	0.38	2.5
Poly-Dielectric		85		2.5	65	8
Poly	125 (50/75)	85	7.8	2.5

Notes

(1)	Thickness calculated from (Pitch/2) * Aspect Ratio, modified with data from reference 2.
(2)	In [7], CVD tungsten is assumed to have a resistivity of 20 uOhm-cm (200 Ohm-nm). The contact and via resistances are calculated from the length and width values of each via, assuming this resistivity.
(3)	Sheet resistances for global and thin-global metal are extrapolated from the value for semi-global metal, assuming the same material and an increase in thickness.

References

[1]	The International Technology Roadmap for Semiconductors (ITRS): Executive Summary, 2005 Edition, p. 5., available online at http://www.itrs.net
[2]	V. Arnal et. al., "45 nm Node Multi Level Interconnects with Porous SiOCH Dielectric k=2.5," Proc. of the IEEE International Interconnect Technology Conference (IITC), pp. 213-215, June 5-7 2006.
[3]	V. Nguyen et. al., "An AnaIysis of the Effect of Wire Resistance on Circuit Level Performance at the 45-nm Technology Node," Proc. of the IEEE International Interconnect Technology Conference (IITC), pp. 191-193, June 6-8 2005.
[4]	S. Narasimha et. al., "High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography," IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[5]	H. Nii et. al., "A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL," IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[6]	N. Oda et. al., "Chip Level Performance Maximization Using ASIS (Application Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Devices", IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 5-7 2005.
[7]	I. Shao et. al., "An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond", IEEE International Interconnect Technology Conference, pp. 102-104, Jun. 4-6 2007.