LAYOUT AND VERIFICATION

Layout Design

To open a new design, select the following from the Library Manager:

File->New->Cell View:
Choose the desired library and cell name, and type `layout' for the View Name and 'Layout’ for the type.

A layout window opens. Also, the Layer Selection Window (LSW) opens at the lefthand side of the screen.
Designing the layout of a circuit consists on selecting the desired layers from the Layer Selection Window and using commands from the following list (keyboard shortcut keys are in brackets):

Creating shapes	Create->Rectangle [r] Create->Path [p]
Editing shapes	Edit->Move [m] Edit->Stretch [s] Edit->Copy [c] Edit->Delete [del] Edit->Properties [q] Edit->Undo [u] Edit->Redo [U]
Measuring distances	Misc->Ruler [k] Misc->Clear Rulers [K]
Window commands	Zoom In [z] Zoom In by 2 [^z] Zoom Out By 2 [Z] Fit All [f] Redraw [^r]
Other commands	Gravity On/Off[g] Display levels (0-20) [F] Display levels (0-0) [^f]

Design Rule Checking (DRC)

At any time during your design, you can verify if any dimensions are being violated.
In the layout window, select:

Verify->DRC...
Set the rules library to: your library (TEST if you are continuing the example from earlier).

The DRC will now run, and if everything is okay, it should finish with the message:

*********   Summary of rule violation for cell "inverter layout"   *********

   Total errors found: 0

If there are errors, the message will contains statistics about which rules were violated. To see where and why, you can use one of the following:

Verify->Markers->Explain:
Click on one of the errors in the layout window. A text window will open with a description.

Verify->Markers->Find:
A dialog window will open. You can use the buttons Apply, Previous and Next to go through the list of errors. If you select the 'Zoom To Markers' button, the layout window will zoom in the respective error.

Extracting the layout:

The extraction tool identifies devices and nodes in the layout. It creates a special view, named `extracted', which contains this information. Later, this view is required for netlist generation, and can be used by a simulator or by the LVS tool.

Verify->Extract...
Again set the rules library to: your library (TEST for example). If you want to include paracitic capacitance in the extraction press the `set switches' button and select "PARASITIC_C". Press OK.

The extraction should finish with the message:

*********   Summary of rule violation for cell "inverter layout"   *********

   Total errors found: 0

If there are any mistakes, you can find about them in the same way that is described above for the DRC. First you have to go to the Library Manager and open the view `extracted' of the cell that you want to simulate.
The rest of the procedure is identical to what was described for schematic simulation. Open the Analog Artist Simulation Window from the Tools menu, and then refer to the section about simulation.

Layout Versus Schematic (LVS)

The LVS tool is used to compare the layout with the schematic, identifying any circuit related differences that might exist between these two views. It reports about circuit nodes and device sizes. You can call the LVS tool from the window containing the layout view or the extracted view. First however we need to setup some LVS parameters.

NCSU->Modify LVS Rules...
Set all the boxes except the Ignore FET Body Terminal.

Now we can run LVS.

Verify->LVS...
The LVS dialog window opens.

Most of the fields should be automatically filled out. Make sure that everything is consistent (view schematic is for schematic netlist and view extracted is for the extracted netlist).
In the Rules File field, type `divaLVS.rul' and the rules library is again your library. Make sure Rewiring, Device Fixing, and Terminals are all selected.

Press the Run button to start the LVS job. Wait until it finishes. A message window will pop-up on the screen when finished.
To see the results of the LVS job, press the Output button. A text window containing the file './LVS/si.out' will open. The result of the comparison is stated in one of three possible sentences:

        1. The net-lists match.

        2. The net-lists failed to match.

        3. The net-lists match logically but

           have mismatched parameters.

In the first case, you can go celebrate. In the second case, one or more nodes in your layout or in your schematic have a mistake. In the third case, all the nodes are correct, but one or more devices have the wrong size.
The output file also contains a list of devices, nodes and terminals for the layout and for the schematic. From this list, you can find how many errors exist, and in which view.

For both of the last two cases, it is necessary to track down the problem. Unfortunately, this is not a straightforward procedure, but more of a debugging process. The following are tools that are available to assist you in this:

In the LVS window, press the Error Display button.

Use the buttons on the top of the window (First, Next, etc) to highlight the errors. You can select which type of error you want to see from the bottom part of the window. Note that the highlighted errors will appear in the "active window". You can make the schematic window or the extracted window active by clicking on one of them. A window is active if the status bar at the top is green.
In the LVS window, press the Info button.

As an example, if you have a merged net in your schematic, you can press the Merged Nets button in the schematic section, and a text window will open with a list of merged nets. Another example: if you have mismatched parameters in your layout, you can press the Audit button in either extracted or schematic sections.
In the extracted window, select Verify->Probe.

If you select the option 'cross probe matched', you can find correspondences between the views. For example, click on one of the nets in your schematic window. The same net will be highlighted in the extracted window.

Simulating the layout:

Refer to the section about simulating the layout in example 2.

Instantiating cells:

To make layout design more simple, it's possible to define blocks which are to be used several times in the same layout. The following example describes how to do this for a transistor.

Design or copy one of your transistors to a separate place. Select the whole transistor and choose:

Edit->Other->Make cell
Fill in a name for the cell, for example, `nmos_10_1', (which stands for w=10u and l=1u, just to keep track of what it is).

You will see the cell as a red outlined box. The contents of this box are now in a different hierarchy level, and can only be accessed with hierarchy commands.

This cell exists now in the library manager. To place more copies in your layout, select:

Create->Instance
Type the name of the library, cell and view, and place it with the mouse.

You can also create arrays of cells, which can be used, for example, to make transistors in parallel. When creating an instance, the form gives you options to change the number of columns or rows, and the distance between the elements.

To return one of the cells to normal layout rectangles, select the cell and use:

Edit->Other->Flatten

Editing hierarchical designs:

When you want to edit a cell, you have to navigate between different hierarchy levels. This is done by selecting the desired cell and using:

Design->Hierarchy->Descend [X]: Descends to cell.
Design->Hierarchy->Edit in Place [x]: Allows editing while looking at the top level.
Design->Hierarchy->Return [B]: Returns to top level.

Of course, you can also edit the cell by opening it from the library manager.

To see all the hierarchy levels, you can use the shortcut key F. To see only the top level, use ^f. This information can be accessed from the menu Design->Options->Display. In the dialog box, there is a field with the `from' and `to' display levels.