Q. Tang, C. Zhou, W. Choi, G. Kang, J. Park, K. Parhi, and C.H. Kim,
"A DRAM based Physical Unclonable Function Capable of Generating >10^32
Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication,"
Proc. 2017 IEEE Custom Integrated Circuits Conference (CICC),
Austin, Texas, April 30-May 3, 2017
K.K. Parhi,
"Analysis of Stochastic Logic Circuits in Unipolar, Bipolar and Hybrid Formats,"
Proc. of 2017 IEEE International Symposium on Circuits and Systems (ISCAS),
Baltimore, Maryland, May 2017
S. Koteshwara, A. Das and K.K. Parhi,
"FPGA Implementation and Comparison of AES-GCM and Deoxys Authenticated Encryption Schemes,"
Proc. of 2017 IEEE International Symposium on Circuits and Systems (ISCAS),
Baltimore, Maryland, May 2017
S. Koteshwara, C.H. Kim, and K.K. Parhi,
"Hierarchical Functional Obfuscation of Integrated Circuits Using a Mode-Based Approach,"
Proc. of 2017 IEEE International Symposium on Circuits and Systems (ISCAS),
Baltimore, Maryland, May 2017
A. Koyily, C. Zhou, C.H. Kim, and K.K. Parhi,
"An Entropy Test for Determining Whether a Mux PUF Is Linear or Nonlinear,"
Proc. of 2017 IEEE International Symposium on Circuits and Systems (ISCAS),
Baltimore, Maryland, May 2017
M. Liu, C. Zhou, Q. Tang, K.K. Parhi, and C.H. Kim,
"A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function,"
Proc. of 2017 ACM/IEEE International Symposium on Low-Power Electronics and Design, Taipei, Taiwan, July 2017
S.V. Sandeep Avvaru, C. Zhou, C.H. Kim and K.K. Parhi,
"Predicting Hard and Soft-Responses and Identifying Stable Challenges of Mux PUFs Using ANN,"
Proc. of 2017 IEEE Midwest Symp. on Circuits and Systems,
Boston, August 2017
S.A. Salehi, M.D. Riedel, and K.K. Parhi,
"Molecular Computation of Complex Markov Chains with Self-Loop State Transitions,"
Proc. 2017 Asilomar Conference on Signals, Systems and Computers,
Pacific Grove, CA, Oct. 29-Nov. 1, 2017
S. Koteshwara, C.H. Kim, and K.K. Parhi,
"Functional Encryption of Integrated Circuits by Key-Based Dynamical Obfuscation,"
Proc. 2017 Asilomar Conference on Signals, Systems and Computers,
Pacific Grove, CA, Oct. 29-Nov. 1, 2017
S. Koteshwara, A. Das and K.K. Parhi,
"Performance Comparison of AES-GCM-SIV and AES-GCM Algorithms for Authenticated Encryption on FPGA Platforms,"
Proc. 2017 Asilomar Conference on Signals, Systems and Computers,
Pacific Grove, CA, Oct. 29-Nov. 1, 2017
G.N.C. Shanmugam, Y. Lao and K.K. Parhi,
"An Obfuscated Radix-2 Real FFT Architecture,"
Proc. of 2015 IEEE Int. Conf. Acoustics, Speech and Signal Processing (ICASSP),
pp. 1056-1060, Brisbane, Australia, April 2015
M. Parhi, Y. Lao and K.K. Parhi,
"Canonic Real-Valued FFT Structures,"
Proc. of 2014 Asilomar Conference on Signals, Systems, and Computers,
pp. 1261-1265, Nov. 2014, Pacific Grove, CA
H. Jiang, M.D. Riedel, and K.K. Parhi,
"Digital Logic with Molecular Reactions,"
Proc. of 2013 IEEE International Conference on Computer Aided Design
(ICCAD), pp. 721-727, San Jose, CA, Nov. 2013
Y. Park, T. Netoff, X. Yang, and K.K. Parhi,
"Seizure Detection On/Off System using Rats' ECoG," Proc. of 2012 IEEE Engineering in
Medicine and Biology Society (EMBC'12),
pp. 4688-4691, San Diego, California, August 28 - September 1, 2012
S. Roychowdhury, D. Koozekanani, and K.K. Parhi,
"Screening Fundus Images for Diabetic Retinopathy,"
Proc. of 46th Asilomar Conference on Signals, Systems and Computers,
pp. 1641-1645, Pacific Grove, CA, Nov. 2012
M.J. Brown, T. Netoff and K.K. Parhi,
"A Low-Complexity Seizure Prediction Algorithm",
Proc. of 33rd Annual International Conference of
the IEEE Engineering in Medicine and Biology Society
(EMBC'11), pp. 1640-1643, Boston, Aug. 2011
A. Shea, B. Fett, M. Riedel, and K.K. Parhi,
"Synthesizing Sequential Register-Based Computation with Biochemistry,"
Proc. of IEEE/ACM International Workshop on Logic Synthesis," 2009
J. Lee, S. Park, Y. Zhang, K.K. Parhi, and S.-C. Park,
"Implementation Issues of a List Sphere Decoder",
Proc. of 2006 IEEE Int. Conf. Acoustics, Speech and Signal Processing,
pp. III-996-III-999, Toulouse (France), May 2006
K. Prasad and K.K. Parhi,
"Low-Power 4-2 and 5-2 Compressors",
Proc. of 2001 Asilomar Conf. on Signals, Systems and
Computers , Vol. 1, pp. 129-133, Nov. 2001
J. Valls, M. Kuhlmann and K.K. Parhi,
"Efficient mapping of CORDIC algorithms on FPGA",
Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS):
Design and Implementation, pp. 336-345, Lafayette, LA, Oct. 2000
M. Kuhlmann, S. Sapatnekar and K.K. Parhi,
"Efficient Crosstalk Estimation",
Proc. of 1999 IEEE Int. Conf. on Computer Design ,
pp. 266-272, Austin, Oct. 1999
T.T. Vu, P.C. Nguyen, L.T. Vu, C.H.
Nguyen, M.D. Bui, A.C. Nguyen, J.N.C. Vu, R. Harjani, K.K. Parhi, D.L.
Polla, R. Schaumann, P.J. Schiller and M.S. Shur,
"Gallium Arsenide Based
Microsensor Systems", Proc. of Government Microcircuit Applications
Conference , March 16-19, 1998, Arlington, Virginia
M. Kuhlmann and K.K. Parhi,
"Power Comparison
of SRT and NST Dividers", Proc. of the SPIE Advanced Signal Processing
Algorithms, Architectures, and Implementations VIII, 1998 Int. Symp. on
Optical Sci., Eng. and Instrumentation , pp. 584-594, July 19-24, 1998, San Diego
(CA)
Y.N. Chang, J. Satyanarayana and K.K.
Parhi,
"Low-Power Digit-Serial Architectures", Proc. of IEEE Int.
Symp. on Circuits and Systems , Vol. 3, pp. 2164-2167, Hong Kong, June 1997
( Invited Talk )
T.T. Vu, P.C. Nguyen,L.T. Vu, C.H. Nguyen,
M.D. Bui, A.C. Nguyen, J.N.C. Vu, R. Harjani, L.L. Kinney, K.K. Parhi,
D.L. Polla, R. Schaumann, P.J. Schiller and M.S. Shur, "Microsensors Fabricated
in Gallium Arsenide", Proc. of Technology 2007 (NASA Tech Briefs,
Federal Laboratory Consortium, and Technology Utilization Foundation) ,
Sept. 22-24, 1997, Boston, MA
V. Sundararajan, M.E. Zervakis and K.K.
Parhi, "Area/Power Efficient Implementation of a Wavelet Domain Robust
Image Denoising System", Proc. of IEEE Workshop on Non-Linear Signal
Processing , Michigan, September 1997
L. Song, K.K. Parhi, I. Kuroda and T.
Nishitani, "Heterogeneous Digit-Serial Finite Field Multipliers and Low-Energy
Reed-Solomon Codecs", Proc. of 35th Annual Allerton Conference
on Communication, Control, and Computing , Illinois, Sept. 29 - Oct.
1, 1997 Invited Talk
K.K. Parhi,
"Fast VLSI Binary Addition", Proc. of 1997 IEEE Workshop on Signal Processing Systems: Design
and Implementation , pp. 232-241, Leicester, U.K., Nov. 1997
Y. Li and K.K. Parhi,
"STAR RLS Lattice
Adaptive Filters", in Proc. of 1996 IEEE Int. Symp. on Circuits
and Systems , pp. II: 389-392, May 1996, Atlanta
D.A. Parker and K.K. Parhi,
"Low Area/Power
Parallel FIR Digital Filters",Proc. of the 1996 Int. Conf. on
Applications-specific Systems, Architectures, and Processors , pp.
93-111, Chicago, August 1996
J.P. Ma, K.K. Parhi, and E.F. Deprettere,
"Pipelining of Cordic Based IIR Digital Filters",
Proc. of ProRISC/IEEE
Workshop , Mierlo, The Netherlands, Nov. 1996
K.J. Raghunath and K.K. Parhi,
"A 100
MHz RLS Adaptive Filter Chip", in Proc. of the 1995 IEEE Int. Conf.
on Acoustics, Speech and Signal Processing , Vol. 5, pp. 3187-3190, May 1995,
Detroit (MI)
K.K. Parhi, "Trading off Concurrency
for Low-Power in Linear and Nonlinear Computations", in Proc. of
1995 IEEE Workshop on Nonlinear Signal Processing , June 1995, pp.
895-898, Thessaloniki, Greece
C.-Y. Wang and K.K. Parhi, "MARS: A
High-Level DSP Synthesis Tool Integrated within the Mentor Graphics
Environment", in Proc. of Mentor Graphics Users' Group Annual Conference ,
October 22-27, 1995, Portland
H.R. Srinivas, and K.K. Parhi,
"A Fast
Radix-4 Division Algorithm", Proc. of 1994 IEEE Int. Symp. on Circuits
and Systems , pp. 4.311-4.314, May 30 - June 2, 1994, London
K.K. Parhi,
"VLSI Digital Signal Processing
Education", Proc. of the 28th Asilomar Conf. on Signals, Systems,
and Computers , Vol. 2, pp. 1303-1308, Oct. 31 - Nov. 2, 1994, Pacific Grove,
CA ( Invited Talk )
G. Shrimali, and K.K. Parhi, "Fast Arithmetic
Decoder Architectures", Proceedings of Sixth SIAM Conference on Parallel
Processing for Scientific Computing , March 22-24, 1993, Norfolk, VA,
pp. 1025-1032
K.K. Parhi, "Algorithms and Architectures
for High-Speed or Low-Power Digital Signal Processing", Proceedings
of the 4th International Conference on Advances in Communications and Control
(COMCON 4) , Rhodes, Greece, June 14-18, 1993, pp. 259-270
K.J. Raghunath, and K.K. Parhi,
"Pipelined
Implementation of High Speed STAR-RLS Adaptive Filters", Proc. of the
SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations
IV, 1993 Int. Symp. on Optical Appl. Sci. and Eng. , Vol. 2027, pp. 122-133, July
11-16, 1993, San Diego (CA), pp. 122-133
N.R. Shanbhag, and K.K. Parhi,
"Pipelined
Adaptive DFE Architectures", Proc. of the SPIE Advanced Signal Processing
Algorithms, Architectures, and Implementations IV, 1993 Int. Symp. on Optical
Appl. Sci. and Eng. , pp. 134-145, Vol. 2027, July 11-16, 1993, San Diego (CA),
pp. 134-145
N.R. Shanbhag, and K.K. Parhi, "Pipelined
Adaptive Quantizers using Relaxed Look-Ahead", in Proc. of the 1993
IEEE Workshop on VLSI in Communications , Sept. 15-17, 1993, Stanford
Sierra Camp, Lake Tahoe, California
H.R. Srinivas, B. Vinnakota, and K.K.
Parhi,
"A C-Testable Carry-Free Divider", Proceedings of the 1993 IEEE
Int. Conf. on Computer Design , October 3-6, 1993, Cambridge, MA, pp.
206-213
N.R. Shanbhag, and K.K. Parhi,
"A Pipelined
Kalman Filter Architecture", Proc. of the 27th Annual Asilomar Conf.
on Signals, Systems, and Computers , Nov. 1-3, 1993, Pacific Grove
(CA), Vol. 2, pp. 1225-1229
K.J. Raghunath, and K.K. Parhi,
"Parallel
Adaptive DFE Algorithms", i n Proc. of the 1992 IEEE Int. Conf. on Acoustics,
Speech, and Signal Processing , March 1992 (San Francisco), pp. IV-353-356
N.R. Shanbhag, and K.K. Parhi,
"A High-Speed
Architecture for ADPCM Codec", in Proc. of the IEEE International
Symposium on Circuits and Systems , San Diego, May 1992, Vol. 3, pp. 1499-1502
N.R. Shanbhag, and K.K. Parhi, "A Pipelined
Adaptive Lattice Filter Architecture", Proc. of the 1992 European Signal
Processing Conference , August 24-28, 1992, Brussels (Belgium), pp.
1057-1060
N.R. Shanbhag, and K.K. Parhi, "A Pipelined
Adaptive Differential Vector Quantizer for Real-Time Video Compression",
Proc. of the IEEE Workshop on Visual Signal Processing and Communications ,
September 1992, Raleigh, North Carolina, pp. 9-14
K.K. Parhi,
"Impact of Architecture
Choices on DSP Circuits", Proc. of the IEEE TENCON: Region 10 Int. Conference
on Computers, Communications, and Automation , Nov. 9-13, 1992, Melbourne,
Australia, pp. 784-788 ( invited talk )
L.E. Lucke, A.P. Brown, and K.K. Parhi,
"Unfolding and Retiming for High-Level Synthesis", in Proc. of 1991
IEEE International Symposium on Circuits and Systems , June 1991, Singapore
( invited talk ), Vol. 4, pp. 2351-2354
K.K. Parhi,
"High-Speed Huffman Decoder
Architectures", in Proc. of Twenty-Fifth Annual Asilomar Conference
on Signals, Systems, and Computers , Nov. 4-6, 1991, Pacific Grove
(CA), Vol. 1, pp. 64-68
N.R. Shanbhag, and K.K. Parhi,
"A Pipelined
LMS Adaptive Filter Architecture", in Proc. of Twenty-Fifth Annual Asilomar
Conference on Signals, Systems, and Computers , Nov. 4-6, 1991, Pacific
Grove (CA), Vol. 2, pp. 668-672
J-G. Chung, and K.K. Parhi,
"Design
of Pipelined Lattice IIR Digital Filters", in Proc. of Twenty-Fifth
Annual Asilomar Conference on Signals, Systems, and Computers , Nov.
4-6, 1991, Pacific Grove (CA), Vol. 2, pp. 1021-1025
K.K. Parhi, and
C.Y. Wang,
"Digit-Serial DSP Architectures", Proceedings of the Third
Conference on Application-Specific Array Processors , September 1990,
Princeton, IEEE Computer Society Press, pp. 341-351
K.K. Parhi and
D.G. Messerschmitt,
"Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding",
Proc. of the 1989 International
Conference on Parallel Processing, August 1989, pp. I:209-216, St.
Charles (Illinois)
K.K. Parhi and
D.G. Messerschmitt, "Block Digital Filtering via Incremental Block-State
Structure", Proceedings of the IEEE International Symposium on Circuits
and Systems, Philadelphia, May 1987, pp. 645-648
K.K. Parhi, W.L.
Chen, and D.G. Messerschmitt, "Architecture Considerations for High Speed
Recursive Filtering", Proceedings of the 1987 IEEE International
Symposium on Circuits and Systems, Philadelphia, May 1987, pp. 374-377
K.K. Parhi and
D.G. Messerschmitt, "Area-Efficient High-Speed VLSI Adaptive Filter Architectures",
Proceedings of the IEEE International Conference on Communications,
Seattle, June 1987, invited talk
1986
K.K. Parhi and
R.S. Berkowitz, "False Alarm Threshold Setting in Complex Multi-Variate
Systems using Importance Sampling Technique", Proceedings of the 29th
Midwest Symposium on Circuits and Systems, Lincoln, Nebraska, August
1986, pp. 227-230
K.K. Parhi and
D.G. Messerschmitt, "A Bit Parallel Bit Level Recursive Filter Architecture",
Proceedings of the IEEE International Conference on Computer Design,
October 6-9, 1986, Rye Town, Rye, NY, pp. 284-289