Release Notes

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Process: Organic Gel-TFT
Contents: OPDK Release Note
File: OPDK_Release_Notes.txt
Created: June 11, 2010
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Release Notes for OPDK 1.5 (2010-12-20)

New in this release:
 - PCell support for TFT & Cap
 - DRAM array example added

Planned for the next release:
 - Revised DRC rules

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Release Notes for OPDK 1.4 (2010-09-06)

New in this release:
 - New CNT-TFT device model w/ hspice model supported

Planned for the next release:
 - PCell support

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Release Notes for OPDK 1.3 (2010-08-23)

New in this release:
 - Example designs of D flip-flop and 3P gain cell
 - Modifided DRC rule
 - Models for TFT

Planned for the next release:
 - Improved model support for CNT TFT

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Release Notes for OPDK 1.2 (2010-06-11)

New in this release:
 - Example designs for tutorial and reusing purpose
 - Hierachical DRC & LVS functionality verified
 - Cadence Virtuoso Analog Design Environment (ADE) netlist creation
   (from schematics) functionality verified for hspiceD and spectre

Planned for the next release:
 - Support for Side-gated TFT structures with P3HT channel

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Release Notes for OPDK 1.1.1 (2010-06-09)

New in this release:
 - Detailed Calibre Design Rules for all supported 25 layers
 - Calibre LVS for top-gated TFT with CNT channel

Rules changed in this release:
 - Calibre LVS TFT Property Macro modified to use channel for W/L
   calculation. Now PEDOT_TFT does not need to exactly fill in the
   gap.
 - Calibre DRC rule for PEDOT_TFT modified according to the LVS TFT
   Property Macro change.
 - Body of TFT can be connected to a common pre-defined SUB layer,
   indicating the substrate (glass, silicon, etc.) of the circuitry.
   SUB layer is easy to handle and hierachical LVS has no trouble now.

Previous issues solved with this release:
 - (Solved) Calibre LVS for top-gated PTFT with P3HT channel requires
   PEDOT_TFT exactly fill in the gap between source/drain electrodes.
   Otherwise, LVS property calculation error can occur.
 - (Solved) Body contact of TFT cannot be eliminated; could introduce
   trouble when doing hierachical LVS check.
Known issues with this release:
 - For high yield, DRC rules are set strict on spacings between PEDOT
   layers and metal. This may introduce unnecessary spacing in design.
   Some of them can be handled by careful placement. Details are illustrated
   on OPDK Webpage.
 - All TFTs need to be defined P or N type in current software environment to
   be correctly recognized. CNT, although neither P nor N type, is defined as
   P type for now.

Planned for the next release:
 - Example designs for tutorial as well as reusing purpose.
 - Verification of hierachical DRC & LVS functionality


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Release Notes for OPDK 1.1 (2010-05-27)

New in this release:
 - Calibre Design Rules for all supported 25 layers
 - Calibre LVS for top-gated PTFT with P3HT channel
 - OPDK_Devices library, with supported device symbols

Known issues with this release:
 - Calibre LVS for top-gated PTFT with P3HT channel requires PEDOT_TFT
   exactly fill in the gap between source/drain electrodes. Otherwise,
   LVS property calculation error can occur.
 - Body contact of TFT cannot be eliminated; could introduce trouble
   when doing hierachical LVS check.

Planned for the next release:
 - More detailed Calibre Design Rules for all 25 supported layers
 - Calibre LVS Rules supporting top-gated TFT with CNT channel

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Release Notes for OPDK 1.0 (2010-05-20)

Included in this release:
 - Technology library and display resources for Cadence Virtuoso 6.1

Planned for the next release:
 - Calibre Design Rules for all 25 supported layers
 - Calibre LVS Rules
 - OPDK_Devices library for device schematic