Architectures
for Binary and Finite Field Arithemtic
We have proposed new architectures
for two's complement arithmetic operations using an internal redundant
number representation. These architectures have been shown to be more
area-efficient than the two's complement architectures. This is because
our architectures can lead to a large savings in the number of pipelining
latches by using our proposed novel redundant-to-two's complement conversion
algorithm. We have proposed an adder architecture which was proved to be
faster than the previously known fastest Brent-Kung binary-look-ahead adder.
A new complex multiply-adder has been developed based on pseudo radix-2
approach.
Residue arithmetic
is being exploited for low-power FIR filter implementations. It is shown
that the smaller moduli can be operated with lower supply voltage leading
to significant power reduction. Efficient modular arithmetic
architectures are being developed and these are being used
to design efficient RSA cryptosystems.
We have proposed efficient
division architectures for radix-2 (with and without prescaling) and radix-4.
In addition, we have proposed radix-2 efficient square-root architectures.
These algorithms are based on redundant and over-redundant number system
representation. In all cases, our algorithms are proven to be faster than
known designs. The impact of these architectures can be understood by one
example. In radix-2 SRT division (proposed in 1960s), the quotient selection
was based on examination of 3 digits of the partial remainder, but we have
proposed an algorithm which can perform quotient selection using only 2
digits of the partial remainder. We have developed a shared divider/square-root
unit based on Svoboda-Tung approach. It may be noted that no square-root
based on Svoboda-Tung approach had been presented before. Low-power divider/square-root
chips have also been designed. Low-power CORDIC rotation
units are also being investigated.
In addition to radix-2
binary arithmetic, we are also pursuing arithmetic architecture design
for finite field (i.e., Galois field) which can be used in error control
coding applications. To this end, we have developed some low-area and low-latency
finite field multipliers, dividers and exponentiation operators. These
operations have been implemented in LSB and MSB first modes and in systolic
and semi-systolic forms. Our proposed architectures lead to low latency
and low power consumption. Efficient Reed-Solomon coders have been developed
based on digit-serial datapaths and appropriate scheduling techniques based
on a hardware-software codesign approach.
Selected
Publications
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H.R. Srinivas, and K.K.
Parhi, "High-Speed VLSI Arithmetic Processor Architectures Using Hybrid
Number Representation", Journal of VLSI Signal Processing, Vol.
4, No. 2/3, 1992, pp. 177-198.
-
H.R. Srinivas, and K.K.
Parhi, "A Fast VLSI Adder Architecture", IEEE Journal of Solid State
Circuits, Vol. 27, No. 5, May 1992, pp. 761-767.
-
H.R. Srinivas, and K.K.
Parhi, "A Fast Radix-4 Division Algorithm", IEEE Transactions on Computers,
44(6), pp. 826-831, June 1995.
-
H.R. Srinivas, K.K. Parhi,
and L. Montalvo, "Radix-2 Division with Over-Redundant Quotient Selection",
IEEE Trans. on Computers, 46(1), pp. 85-92, Jan. 1997
-
L. Montalvo, K.K. Parhi,
and A. Guyot, "New Svoboda-Tung Division", IEEE Trans. on Computers,
47(9), Sept. 1998
-
S. Jain, L. Song and K.K.
Parhi, "Efficient Semi-Systolic VLSI Architectures for Finite Field Arithmetic",
IEEE Trans. on VLSI Systems , f6(1), pp. 101-113, March 1998
-
L. Song and K.K. Parhi,
"Low-Energy Digit-Serial/Parallel Finite Field Multipliers", Journal
of VLSI Signal Processing, 19(2), pp. 149-166, June 1998
-
L. Montalvo and K.K. Parhi,
"Radix-2 Over-Redundant Digit-Set Convereters", in Proc. of 1996 IEEE
Int. Symp. on Circuits and Systems , pp. 81-84, May 1996, Atlanta
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L. Song and K.K. Parhi,
"Low-Area Dual-Basis Divider Over $GF(2^M)$", Proc. of IEEE Int. Conf.
on Acoustics, Speech and Signal Processing , pp. 627-530, Munich, April
1997
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K.K. Parhi, "Fast Low-Energy
VLSI Binary Addition", Proc. of IEEE Conf. on Computer Design ,
pp. 676-684, Austin, October 12-15, 1997
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W. Freking and K.K. Parhi,
"Low-Power Digital Filters using Residue Arithmetic", Proc. of 1997
Asilomar Conf. on Signals, Systems and Computers , pp. 739-743, November
1997 Invited Talk
-
L. Song and K.K. Parhi,
"Optimum Primitive Polynominals for Low Area and Low Power Finite Field
Semi-Systolic Multipliers", Proc. of 1997 IEEE Workshop on Signal Processing
Systems: Design and Implementation , pp. 375-384, Leicester, U.K.,
Nov. 1997
-
L. Song, K.K. Parhi, I.
Kuroda, and T. Nishitani, "Low-energy Heterogeneous Digit-Serial Reed-Solomon
Codecs", in Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal
Processing , pp. 3049-3052, May 1998, Seattle
-
L. Song, K.K. Parhi, I.
Kuroda and T. Nishitani, "Low-Energy Programmable Finite Field Datapath
Architectures", Proc. of IEEE Int. Symp. on Circuits and Systems
, pp. II-406-II-409, Monterey, May 31 - June 3, 1998
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L. Song, K.K. Parhi, I.
Kuroda and T. Nishitani, "Low-Energy Programmable Finite Field Datapath
Architectures", Proc. of IEEE Int. Symp. on Circuits and Systems
, pp. II-406-II-409, Monterey, May 31 - June 3, 1998
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L. Song and K.K. Parhi,
"Scheduling Stragegies for Low-Energy Programmable Digit-Serial Reed-Solomon
Codecs", Proc. of 1998 IEEE Workshop on Signal Processing Systems: Design
and Implementations (SiPS) , Oct. 8-10, 1998, Boston
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M. Kuhlmann and K.K. Parhi,
"Fast Low-Power Shared Division and Sqaure-Root Architecture", Proc.
of 1998 IEEE Int. Conf. on Computer Design , Austin, Oct. 1998
-
W. Freking and K.K. Parhi,
"Parallel Modular Multiplication with Application to VLSI RSA
Implementation",
Proc. of 1999 Int. Symp. on Circuits and Systems, Orlando,
June 1999
-
L. Song and K.K. Parhi,
"Low-Energy Software Reed-Solomon Codecs Using Specialized Finite Field
Datapath and Division-Free Berlekamp-Massey Algorithm",
Proc. of 1999 Int. Symp. on Circuits and Systems, Orlando,
June 1999
-
L. Song and K.K. Parhi,
"Low-Complexity Modified Mastrovito Multipliers over Finite Fields
GF(2**m)",
Proc. of 1999 Int. Symp. on Circuits and Systems, Orlando,
June 1999
-
Y.N. Chang and K.K. Parhi,
"High-Performance Digit-Serial Complex-Number Multiplier-Accumulator",
Proc. of 1998 IEEE Int. Conf. on Computer Design , Austin, Oct.
1998
[Bac
k page] [Prof.
Parhi's homepage]